Hi,
I'm using Arm Pro C compiler v6.2.0
Trying to use STM32F401C for black pill, made a simple led flash prog, downloaded it, nothing happens (but I'm an old hand at various other 1xx, 4xx, 7xx series arm chips)
While checking out the RCC regs as setup by Edit Prog pop up I noticed that PPRE1 (bits 12:10) and PPRE2 (bits 15:13) are set wrong. I configured for PPRE1=div4 (bits=101) and PPRE2=dic2 (bits= 100)
but the mikroe app is setting these as 001 and 001 which looks like no divide. Tried for other divs but all give wrong bits - it's late at night - am I reading this wrong or is there an actual error in the
edit prog app for this micro ?
Tried same settings for a clicker2 module stm32F407 - this gave RCC_CFGR as 0x00609402 (correct and working)
Same setting for stm32F401 gave 0x00602502 which is wrong.
STM32F401CC RCC config regs wrong ?
General discussion on mikroC PRO for ARM.
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Re: STM32F401CC RCC config regs wrong ?
#2 Post by SteveH » 27 Sep 2022 18:48
A bit more work on this problem this evening.
Definitely looks like the mikroe edit prog is creating the correct bit fields for PPRE1 and PPRE2 but is not formatting them correctly together to make the RCC_CFGR 32 bit long word.
It seems that both PPRE1 and PPRE2 are wrongly shifted right 2 places, bit 11 is always 0, plus lower bits of PPRE2 over spill into RCC_CFGR bits 9,8 which are reserved and should be 0
i.e PPRE2 PPRE1
2 1 0 . 2 1 0
| | | | | |
0 0 | | 0 | | |
RCC_CFGR 15 14 13 12 11 10 09 08
Need to be like this to work correctly
PPRE2 PPRE1
2 1 0 . 2 1 0
| | | | | |
| | | | | | 0 0
RCC_CFGR 15 14 13 12 11 10 09 08
Definitely looks like the mikroe edit prog is creating the correct bit fields for PPRE1 and PPRE2 but is not formatting them correctly together to make the RCC_CFGR 32 bit long word.
It seems that both PPRE1 and PPRE2 are wrongly shifted right 2 places, bit 11 is always 0, plus lower bits of PPRE2 over spill into RCC_CFGR bits 9,8 which are reserved and should be 0
i.e PPRE2 PPRE1
2 1 0 . 2 1 0
| | | | | |
0 0 | | 0 | | |
RCC_CFGR 15 14 13 12 11 10 09 08
Need to be like this to work correctly
PPRE2 PPRE1
2 1 0 . 2 1 0
| | | | | |
| | | | | | 0 0
RCC_CFGR 15 14 13 12 11 10 09 08
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