Timer 0, reload value question

[Dany]

Hi, see the following quote. My question is: is the reasoning in it correct or not? It is about the tool "PIC Timer Calculator" and the way to handle "preload" values for Timer 0. I posed the question to the tool builder, but I did not get a reply yet, so I want to know how things actually are concerning Timer0 reload.
Thanks in advance.

Hi, I think I have detected a few problems with the "TMR0 Adjust" feature in the PIC Timer Calculator (I think ), v0.9.0. (still present in v0.9.2)

1. If one activates this feature then the TMR0 "preload" value is decremented by 2. I think it should be incremented by 2 in stead. The reason is that 2 cycles are skipped by timer0, resulting in a longer delay to next rollover. To compensate for this the preload value should be 2 higher than normal.

Extract from the "MID Range Manual", section Timer0:

Any write to the TMR0 register will cause a 2 instruction cycle (2TCY) inhibit. That is, after the
TMR0 register has been written with the new value, TMR0 will not be incremented until the third
instruction cycle later (Figure 11-2).

and (from the "Design tips"):

When writing to TMR0, two instruction clock cycles are lost. Often you have a specific time period you want to count, say 100 decimal. In that case you might put 156 into TMR0 (256 - 100 = 156). However, since two instruction cycles are lost when you write to TMR0 (for internal logic synchronization), you should actually write 158 to the timer.

2. The correction in the "preload" value does not take into account if the prescaler is used. The correction in this preload value should be multiplied by the division caused by the prescaler (so, if the prescaler is at 1:4, then the correction should be 4 times 2 units).

Extract from the "MID Range Manual", section Timer0:

When the prescaler is assigned to the Timer0 module, any
write to the TMR0 register will immediately update the TMR0 register and clear the prescaler. The
incrementing of Timer0 (TMR0 and Prescaler) will also be inhibited 2 instruction cycles (TCY). So
if the prescaler is configured as 2, then after a write to the TMR0 register TMR0 will not increment
for 4 Timer0 clocks (Figure 11-3). After that, TMR0 will increment every prescaler number of
clocks later.

By the way: GREAT TOOL!

[janni]

2. The correction in the "preload" value does not take into account if the prescaler is used. The correction in this preload value should be multiplied by the division caused by the prescaler (so, if the prescaler is at 1:4, then the correction should be 4 times 2 units).

Nope. You go too far here. The delay will be still 2Tcy. The explanation in MID Range Manual is not very good, but from Figure 11-3 one may conclude that both Timer0 and prescaler start working normally after 2Tcy (i.e. Timer0 increments every 2nd instruction clock).

In other words, for 1:2 prescaler, one has to increase the preload value by 1. For 1:4 prescaler, one would have to increase the preload value by 1/2 count (tough one ), or by 1 count every second preload.

[Dany]

2. The correction in the "preload" value does not take into account if the prescaler is used. The correction in this preload value should be multiplied by the division caused by the prescaler (so, if the prescaler is at 1:4, then the correction should be 4 times 2 units).

Nope. You go too far here. The delay will be still 2Tcy. The explanation in MID Range Manual is not very good, but from Figure 11-3 one may conclude that both Timer0 and prescaler start working normally after 2Tcy (i.e. Timer0 increments every 2nd instruction clock).

In other words, for 1:2 prescaler, one has to increase the preload value by 1. For 1:4 prescaler, one would have to increase the preload value by 1/2 count (tough one ), or by 1 count every second preload.

Hi Janni, thanks. Sounds logical, but the MID Range Manual is actually wrong then (see its example).
You did not comment on point 1. Is the reasoning about the preload correction OK there?
Thanks in advance.

[janni]

MID Range Manual is actually wrong then (see its example).

Which example?

You did not comment on point 1. Is the reasoning about the preload correction OK there?

Yep . That's why I didn't comment it.

[Dany]

MID Range Manual is actually wrong then (see its example).

Which example?

This one:

When the prescaler is assigned to the Timer0 module, any
write to the TMR0 register will immediately update the TMR0 register and clear the prescaler. The incrementing of Timer0 (TMR0 and Prescaler) will also be inhibited 2 instruction cycles (TCY). So if the prescaler is configured as 2, then after a write to the TMR0 register TMR0 will not increment for 4 Timer0 clocks (Figure 11-3). After that, TMR0 will increment every prescaler number of clocks later.

It suggests that the number of inhibited cycles (normally 2) has to be multiplied by the prescaler value. Or does it not suggest that?

You did not comment on point 1. Is the reasoning about the preload correction OK there?

Yep . That's why I didn't comment it.

Thanks.

[janni]

It suggests that the number of inhibited cycles (normally 2) has to be multiplied by the prescaler value. Or does it not suggest that?

No, it does not, but the wording is indeed unfortunate. If you compare the diagrams for no prescaler and prescaler 1:2, you'll see that in the latter case there's only one instruction cycle more with unchanged Timer0 value.

[Dany]

Thanks Janni.