See the figure below which shows that the data pulse drops when the clock rises. The first row (Channel 0) is chip enable which is low, second row (Channel 1) is data, third row (Channel 2) is clock.
There should be more overlap of data high and the rising edge of clock so that the slave device can correctly detect the data state. Also, clock is not 50% duty cycle which I am used to seeing.
Is there a way to delay the data pulse relative to the clock pulse in the SoftSPI library?
ANY SUGGESTIONS?
We are the PIC Basic Pro compiler and a 16F1705 PIC.
