I have a project to interface a touchscreen GLCD CFAG320240CX-TFH-T-TS (It has a built-in Epson S1D13700 controller) with PIC32MX795F512L.
I am using C coding, MPLAB version 8.92 IDE, MPLAB C32 C compiler.
I have also tried using MPLABX and XC32 compiler.
I have referred the datasheet of the GLCD and also the S1D13700 Technical manual and followed the initialization example steps mentioned in the datasheet to write a similar code.
Unfortunately, I’m not able to display anything on the display, tried changing my board and used different LCDs with the same controller; still there is absolutely nothing on my display. So, I again doubt if the coding is not proper.
My primary task is to display characters which I send to be displayed on the screen.
DETAILS :
Processor: PIC32MX795F512L
Coding Language: C language
IDE: MPLAB version 8.92 IDE
Compiler: MPLAB C32 C compiler
Touchscreen GLCD: CFAG320240CX-TFH-T-TS (built-in Epson S1D13700 controller)
In the touchscreen GLCD, I have set the jumper position to choose 6800 mode, indirect addressing. So, the following pins are use for interfacing GLCD to PIC:
DATA port : PORT E
CONTROL port : PORT D
LCD_RESET :RD2
LCD_CS :RD4
LCD_EN :RD1
LCD_WR :RD3
LCD_A0 :RD5
LCD_DISP :RD6
LCD_WAIT :RD7
Is there any other tools needed for the programming?
Any documents describing the basic steps of how to proceed, sample C codes or links to other useful posts in this area would be helpful.
Please do mail me your suggestions or any sample codes at the earliest.
I have absolutely no idea of how to proceed further.
Could someone please go through the code and check if any mistake from my part as I'm a beginner in this area.
A sample of my C code:
Code: Select all
#pragma config FNOSC = PRIPLL // Oscillator Selection
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (KLO was off)
#pragma config POSCMOD = HS // Primary Oscillator
#pragma config OSCIOFNC = ON // CLKO Enable
#pragma config FPBDIV = DIV_4 // Peripheral Clock divisor
#pragma config FPLLIDIV = DIV_2 // PLL Input Divider
#pragma config FPLLMUL = MUL_20 // PLL Multiplier
#pragma config FPLLODIV = DIV_1 // PLL Output Divider
#pragma config FWDTEN = OFF // Watchdog Timer Disable
#pragma config DEBUG = ON // Background Debugger Enable
#include <p32xxxx.h>
#include <plib.h>
#define S1D13700_DATA_PORT LATE
#define S1D13700_DATA_DIR TRISE
#define S1D13700_DATA_PIN PORTE
#define S1D13700_CONTROL_PORT LATD
#define S1D13700_CONTROL_DIR TRISD
#define S1D13700_CONTROL_PIN PORTD
#define S1D13700_A0 (1<<5) // controller card
#define S1D13700_WR (1<<3)
#define S1D13700_CS (1<<4)
#define S1D13700_RES (1<<2)
#define S1D13700_EN (1<<1)
#define CLR_A0 PORTD &= ~(S1D13700_A0);
#define SET_A0 PORTD |= (S1D13700_A0);
#define CLR_WR PORTD &= ~(S1D13700_WR);
#define SET_WR PORTD |= (S1D13700_WR);
#define CLR_CS PORTD &= ~(S1D13700_CS);
#define SET_CS PORTD |= (S1D13700_CS);
#define CLR_RESET PORTD &= ~(S1D13700_RES);
#define SET_RESET PORTD |= (S1D13700_RES);
#define CLR_EN PORTD &= ~(S1D13700_EN);
#define SET_EN PORTD |= (S1D13700_EN);
#define CPU_CLOCK 8000000
#define __delay_1ms() (CPU_CLOCK/4000000)
//#define __delay_10us() (CPU_CLOCK/4000000)
// Function prototypes
void write_command(unsigned char command);
void write_data(unsigned char data);
void ClearTextLayer(void);
void ClearGraphicLayer(void);
void Delay100uS(unsigned int);
void initialize_display(void);
void HardReset(void);
void write_command(unsigned char command)
{
/* RESET and CS pins are active low
E:0 = No operation
1 = Enable for Read or Write
R/W:1 = Read
0 = Write
A0:When R/W = L
A0 = H: Command Write
A0 = L: Data Write
A0:When R/W = H
A0 = H: Status Read
A0 = Data Read
CS:Chip select, Active L
RES:Controller reset signal, Active L
DISPOFF:H= Display
L= No Display
WAIT:S1D13700F01 controller busy status
*/
S1D13700_DATA_PIN = command;// write the command to the port
SET_A0;
CLR_CS; // chip selected
//SET_RS; // set to write to the control registers
CLR_WR; // writing
SET_EN; // clock in the command
CLR_EN; // bring write line low
SET_CS; // unselect chip
//SET_RS; // set for data
}
void write_data(unsigned char data)
{
S1D13700_DATA_PIN = data;// write the command to the port
CLR_A0;
CLR_CS; // chip selected
//CLR_RS; // set to write to the control registers
CLR_WR; // writing
SET_EN; // clock in the command
CLR_EN; // bring write line low
SET_CS; // unselect chip
//SET_RS; // set for data
}
void initialize_display()
{
HardReset();
CLR_EN;
//CLR_RS;
SET_CS;
S1D13700_DATA_PIN=0x00;
SET_RESET;
delay_ms(10);
CLR_RESET;
delay_ms(100);
SET_RESET;
delay_ms(500);
//SYSTEM_SET:
write_command(0x40);
write_data(0x30); // REG[00h] Memory Configuration Register
// 0011 0000
// |||| ||||-- bit 0: Character Generator Select (M0)
// |||| ||| 0=the internal CGROM is selected.
// |||| ||| 1=the internal CGRAM is selected.
// |||| |||--- bit 1 Reserved = 0
// |||| ||---- bit 2 Character Height (M2)
// |||| | When this bit = 0, the character height is 8 pixels.
// |||| | When this bit = 1, the character height is 16 pixels.
// |||| |----- bit 3 Panel Drive Select (W/S)
// |||| When this bit = 0, a single panel drive is selected.
// |||| When this bit = 1, a dual panel drive is selected.
// ||||
// ||||------- bit 4 Reserved = 1
// |||-------- bit 5 Screen Origin Compensation (IV)
// || When this bit = 0, screen origin compensation is done.
// || When this bit = 1, screen origin compensation is not done.
// ||--------- bit 6 unused = 0
// |---------- bit 7 unused = 0
write_data(0x87); //FX= REG[01h] Horizontal Character Size Register
// 1000 0111
// |||| ||||-- Horizontal Character Size (FX) bits 0-3
// |||| These bits define the horizontal size, or width, of each character, in pixels.
// |||| REG[01h] bits 3-0 = Horizontal Character Size in pixels - 1
// ||||------- bit 4,5,6 unused = 0
// |---------- bit 7 MOD
// When this bit = 0, 16-line AC drive is selected.
// When this bit = 1, two-frame AC drive is selected.
write_data(0x07); //FY= REG[02h] Vertical Character Size Register
// 0000 0111
// |||| ||||-- Vertical Character Size (FY) bits 0-3
// |||| These bits define the vertical size, or height, of each character, in pixels.
// |||| REG[02h] bits 3-0 = Vertical Character Size in pixels - 1
// ||||------- bits 4-7 unused = 0
write_data(39); //C/R= REG[03h] Character Bytes Per Row Register
// These bits determine the size of each character row (or display line), in bytes,
// to a maximum of 239. The value of these bits is defined in terms of C/R
// REG[03h] bits 7-0 = ([C/R] x bpp) - 1 (bpp == bits per pixel)
//
// C/R =(320 dots / 8 dots/character) = 40
// 2 bpp = 80
// REG[03h] = [C/R] x bpp) - 1 = 79
write_data(41); //TC/R=REG[04h] Total Character Bytes Per Row Register
// These bits set the length of one line, including horizontal blanking, in bytes,
// to a maximum of 255. The value of these bits is defined in terms of TC/R TC/R
// can be adjusted to hold the frame period constant and minimize jitter for any
// given main oscillator frequency, fosc.
// REG[04h] bits 7-0 = [TC/R] + 1
// TC/R must be programmed such that the following formulas are valid.
// [C/R] + 2 <= [TC/R]
// 0 <= [TC/R] <= 255
write_data(239); //L/F= REG[05h] Frame Height Register
// These bits determine the frame height, in lines. The maximum frame height is
// 256 lines.
// REG[05h] bits 7-0 = frame height in lines - 1.
// 240 lines in this module, so REG[05h] = 240-1 = 239
write_data(0x28); //APL= REG[06h] Horizontal Address Range Register 0
write_data(0x00); //APH= REG[07h] Horizontal Address Range Register 1
// These bits define the horizontal address range of the virtual screen.
// The maximum value for this register is 7FFFh.
// REG[07h] bits 7-0, REG[06h] bits 7-0 = Addresses per line
// Number of bytes used for one line = 80 = 0x0050
//SCROLL:
write_command(0x44);
write_data(0x00); // REG[0Bh] Screen Block 1 Start Address Register 0
write_data(0x00); // REG[0Ch] Screen Block 1 Start Address Register 1
// Screen Block 1 Start Address (SAD1) bits [15:0]
// These bits determine the memory start address of screen block 1.
write_data(239); // REG[0Dh] Screen Block 1 Size Register
// These bits determine the size of screen block 1, in lines.
// REG[0Dh] bits 7-0 = screen block 1 size in number of lines - 1
// 240 lines - 1 = 239
write_data(0x60); // REG[0Eh] Screen Block 2 Start Address Register 0
write_data(0x09); // REG[0Fh] Screen Block 2 Start Address Register 1
// These bits determine the memory start address of screen block 2.
// 0x0960
write_data(239); // REG[10h] Screen Block 2 Size Register
// These bits determine the size of screen block 2, in lines.
// REG[10h] bits 7-0 = screen block 2 size in number of lines - 1
// 240 lines - 1 = 239
write_data(0x00); // REG[11h] Screen Block 3 Start Address Register 0
write_data(0x00); // REG[12h] Screen Block 3 Start Address Register 1
// These bits determine the memory start address of screen block 3.
// 0x0000
write_data(0x00); // REG[13h] Screen Block 4 Start Address Register 0
write_data(0x00); // REG[14h] Screen Block 4 Start Address Register 1
// These bits determine the memory start address of screen block 4.
// 0x0000
//HDOT_SCR:
write_command(0x5A); // REG[1Bh] Horizontal Pixel Scroll Register
write_data(0x00); //NO SCROLL
// 0000 0000
// |||| ||||-- Horizontal Pixel Scroll bit 1 - 3
// |||| |----- bit 3-7 unused = 0
// These bits specify the number of horizontal pixels to scroll the display.
// The character bytes per row (C/R), REG[03h] bits 7-0, must be set to one
// more than the actual number of horizontal characters before using horizontal
// pixel scroll. Smooth scrolling can be simulated by repeatedly changing the
// value of REG[1Bh] bits 2-0.
//OVERLAY: (Note: Screen blocks 2 and 4 can display graphics only.)
write_command(0x5B); // REG[18h] Overlay Register
write_data(0x01); //GRAPHIC & XOR
// 0000 0001
// |||| ||||-- bit 0 Layer Composition Method (MX) bit 1
// |||| |||--- bit 1 Layer Composition Method (MX) bit 2
// |||| || These bits select the layered screen composition method,
// |||| || which can be OR, AND, or Exclusive-OR.
// |||| ||
// |||| ||---- bit 2 Screen Block 1 Display Mode (DM0)
// |||| | This bit determines the display mode for screen block 1.
// |||| | When this bit = 0, screen block 1 is configured for text mode.
// |||| | When this bit = 1, screen block 1 is configured for graphics mode.
// |||| |
// |||| |----- bit 3 Screen Block 3 Display Mode (DM1)
// |||| This bit determines the display mode for screen block 3.
// |||| When this bit = 0, screen block 3 is configured for text mode.
// |||| When this bit = 1, screen block 3 is configured for graphics mode.
// ||||
// ||||------- bit 4 3 Layer Overlay Select (OV)
// ||| This bit determines how many layers are used when graphics mode is enabled.
// ||| - For mixed text and graphics, this bit must be set to 0.
// ||| When this bit = 0, two layers are used.
// ||| When this bit = 1, three layers are used.
// |||
// |||-------- bit 5-7 unused = 0
// DISP-ON/OFF Settings
write_command(0x58); // DISP ON/OFF-Enables/disables display and display attributes(58h&59h)
//Delay100uS(140);
write_data(0x56); // Enable layer1 and layer2
//Delay100uS(140);
ClearTextLayer(); // Clear main layer1
//Delay100uS(140);
ClearGraphicLayer(); // Clear main layer2
//Delay100uS(140);
//CSRW
write_command(0x46); // CSRW
//Delay100uS(140);
write_data(0x00); //
//Delay100uS(140);
write_data(0x00); //
//Delay100uS(140);
//CSR_FORM:
write_command(0x5D);
write_data(0x06); // REG[15h] Cursor Width Register
// 0000 0110
// |||| ||||-- bit 0 Cursor Width (CRX) bit 0-3
// |||| These bits specify the width (or horizontal size) of the cursor, in pixels from
// |||| the character origin
// |||| REG[15h] bits 3-0 = cursor width in pixels - 1
// ||||
// ||||------- bit 4-7 unused = 0
write_data(0x86); // REG[16h] Cursor Height Register
// 1000 0110
// |||| ||||-- bit 0 Cursor Height (CRY) bit 0
// |||| |||--- bit 1 Cursor Height (CRY) bit 1
// |||| ||---- bit 2 Cursor Height (CRY) bit 2
// |||| |----- bit 3 Cursor Height (CRY) bit 3
// |||| For an underscore cursor (REG[16h] bit 7 = 0), these bits set the location
// |||| of the cursor, in lines from the character origin.
// |||| For a block cursor (REG[16h] bit 7 = 1), these bits set the height
// |||| (or vertical size) of the cursor, in lines from the character origin.
// |||| REG[16h] bits 3-0 = cursor height in lines - 1
// ||||
// ||||------- bit 4-7 unused = 0
// This bit determines the cursor mode. When graphics mode is selected,
// this bit must be set to 1.
// When this bit = 0, an underscore cursor ( _ ) is selected.
// When this bit = 1, a block cursor ( ¦ ) is selected.
// DISP-ON/OFF Settings
write_command(0x59); // DISP ON/OFF-Enables/disables display and display attributes(58h&59h)
//Delay100uS(140);
write_data(0x14); // REG[0Ah] Display Attribute Register values
// 0001 0000
// |||| ||||-- bit 0 Cursor Attribute (FC) bit 0
// |||| |||--- bit 1 Cursor Attribute (FC) bit 1
// |||| || These bits control the cursor and set the flash rate -- 70% duty cycle (70% on, 30% off):
// |||| || 0 0 OFF (Blank)
// |||| || 0 1 ON No Flashing
// |||| || 1 0 ON Flash at fFR/32 Hz (approx. 2 Hz)
// |||| || 1 1 ON Flash at fFR/64 Hz (approx. 1 Hz)
// |||| || NOTE: When the cursor is disabled, a write to memory automatically enables the cursor and
// |||| || places the cursor at the next memory location. A read from memory does not enable the
// |||| || cursor, however, it still places the cursor at the next memory location.
// |||| ||
// |||| ||---- bit 2 SAD1 Attribute (FP 1-0) bit 0
// |||| |----- bit 3 SAD1 Attribute (FP 1-0) bit 1
// |||| These bits control the attributes of the third screen block (SAD1):
// |||| 0 0 OFF (Blank)
// |||| 0 1 ON No Flashing
// |||| 1 0 ON Flash at fFR/32 Hz (approx. 2 Hz)
// |||| 1 1 ON Flash at fFR/4 Hz (approx. 16 Hz)
// ||||
// ||||------- bit 4 SAD2 Attribute (FP 3-2) bit 0
// |||-------- bit 5 SAD2 Attribute (FP 3-2) bit 1
// || These bits control the attributes of the third screen block (SAD2):
// || 0 0 OFF (Blank)
// || 0 1 ON No Flashing
// || 1 0 ON Flash at fFR/32 Hz (approx. 2 Hz)
// || 1 1 ON Flash at fFR/4 Hz (approx. 16 Hz)
// ||
// ||--------- bit 6 SAD3 Attribute (FP 5-4) bit 0
// |---------- bit 7 SAD3 Attribute (FP 5-4) bit 1
// These bits control the attributes of the third screen block (SAD3):
// 0 0 OFF (Blank)
// 0 1 ON No Flashing
// 1 0 ON Flash at fFR/32 Hz (approx. 2 Hz)
// 1 1 ON Flash at fFR/4 Hz (approx. 16 Hz)
//CSR_DIR:
write_command(0x4C); // REG[17h] Cursor Shift Direction Register -- Default = 00h
// 0100 11dd
// |||| ||||-- bit 1:0
// |||| || 0 0 Right (command 0x4C)
// |||| || 0 1 Left (command 0x4D)
// |||| || 1 0 Up (command 0x4E)
// |||| || 1 1 Down (command 0x4F)
// ||||-||---- bit 2-7 (command 0x4C base)
//MWRITE
write_command(0x42);
//Delay100uS(140);
write_data(0x20); //''
//Delay100uS(140);
write_data(0x45); //‘E’
//Delay100uS(140);
write_data(0x50); //‘P’
//Delay100uS(140);
write_data(0x53); //‘S’
//Delay100uS(140);
write_data(0x4F); //‘O’
//Delay100uS(140);
write_data(0x4E); //‘N’
//Delay100uS(140);
}
void ClearTextLayer(void)
{
int i;
write_command(0x46);
write_data(0x00);
write_data(0x00);
write_command(0x42);
CLR_A0;
CLR_CS;
for(i=0;i<((0x28)*30);i++)
{
write_data(0x20);
SET_EN;
CLR_EN;
}
SET_CS;
}
void ClearGraphicLayer(void)
{
int i;
write_command(0x46);
write_data(0x60);
write_data(0x09);
write_command(0x42);
CLR_A0;
CLR_CS;
for(i=0;i<((0x28)*240);i++)
{
write_data(0x00);
SET_EN;
CLR_EN;
}
SET_CS;
}
void delay_ms(unsigned int ms)
{
while(ms--)
{
__delay_1ms();
}
}
void HardReset(void)
{
//S1D13700_CONTROL_DIR &= ~(S1D13700_RES);
S1D13700_CONTROL_PIN &= ~(S1D13700_RES);
delay_ms(3);
// S1D13700_CONTROL_DIR |= (S1D13700_RES);
S1D13700_CONTROL_PIN |= (S1D13700_RES);
delay_ms(10);
}
int main()
{
mPORTDSetPinsDigitalOut(BIT_6); //Set RD6 configured as LCD DISPLAY to output
mPORTDSetBits(BIT_6);
S1D13700_DATA_DIR = 0x00;
//TRISE=0;
//mPORTESetPinsDigitalOut(BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
//mPORTDSetPinsDigitalOut(BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1);
S1D13700_CONTROL_PORT |= (S1D13700_A0 | S1D13700_WR | S1D13700_CS | S1D13700_RES |S1D13700_EN);
S1D13700_CONTROL_DIR &= ~(S1D13700_A0 | S1D13700_WR | S1D13700_CS | S1D13700_RES |S1D13700_EN);
initialize_display();
}
Thanks in advance.
