The LFSR instruction is wrongly coded for K42 and K83 processors (same will go for Qxx families if, by some miracle, they'll be implemented) as for these processors the address field is 14, not 12-bits wide.
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asm LFSR 0,0x800; // FSR0 points to 0x2000 in K42 and K83 processors
0xF000EE08 LFSR 0, 2048
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0xF000EE02 LFSR 0, 2048
It's probably not worth mentioning that the ADDFSR, SUBFSR and CALLW instructions were never implemented .
BTW, there's also an old quirk that prevents using constants in the LFSR instruction - compiler looses higher address byte in such case:
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const addr=0x800;
main(){
asm LFSR 0,_addr;// higher byte of addr is lost
0xF000EE00 LFSR 0, 0