Solved(With DMA) : How to access more than 16 ADC Channels?

[s_sergiu]

Hi,

I have one project where I need to use 21 ADC channels.
I use STM32F429. I need to use all inputs of ADC3.
How to access them from mikrobasik?

Sergiu

[danilo.milovic]

Hi,

please read http://download.mikroe.com/documents/co ... ut_channel

ADC_Set_Input_Channel(_ADC_CHANNEL_X);

Regards,

Danilo

[s_sergiu]

Hi Danilo,

I seen that example.
However I don't see how it will work when you have for example ADC12_IN7 and ADC3_IN7 or ADC12_IN14 and ADC3_IN14
Both have same IN# but in different ADC's.
However one work around is by using DMA :


'*******************************************************************************
Dim adcr as longword[24] ' result of ADC conversion is stored here

sub procedure ADC_DMA() iv IVT_INT_DMA2_Stream0 ics ICS_AUTO

' Stop the ADC's so we have time to process the samples in main loop
ADC1_CR2.ADON = 0
ADC2_CR2.ADON = 0
ADC3_CR2.ADON = 0
DMA2_LIFCR.CTCIF0 = 1 ' clear DMA2 interrupt or it will not start again.
ADC_READY = 1 ' flag to inform program that ADC conversion has completed
DMA2_S0CR.EN = 1 ' enable DMA2 Stream0 again for next transfer

end sub
'*******************************************************************************
'*******************************************************************************
'*******************************************************************************
sub procedure ADC_INIT()

Rem Enable Peripheral ADC1,ADC2 and ADC3 Clock's
RCC_APB2ENR.ADC1EN=1
RCC_APB2ENR.ADC2EN=1
RCC_APB2ENR.ADC3EN=1
'*************************************************
rem Enable GPIO Port_A, Port_C and Port_F clock's
RCC_AHB1ENR.GPIOAEN=1
RCC_AHB1ENR.GPIOBEN=1
RCC_AHB1ENR.GPIOCEN=1
RCC_AHB1ENR.GPIOFEN=1
'*************************************************
rem Configure GPIO Port_A, Port_F and Port_C for ADC input;
GPIO_Analog_Input(@GPIOF_BASE, _GPIO_PINMASK_3 or _GPIO_PINMASK_4 or _GPIO_PINMASK_5)
GPIO_Analog_Input(@GPIOF_BASE, _GPIO_PINMASK_6 or _GPIO_PINMASK_7 or _GPIO_PINMASK_8)
GPIO_Analog_Input(@GPIOF_BASE, _GPIO_PINMASK_9 or _GPIO_PINMASK_10)
GPIO_Analog_Input(@GPIOC_BASE, _GPIO_PINMASK_0 or _GPIO_PINMASK_1 or _GPIO_PINMASK_2)
GPIO_Analog_Input(@GPIOC_BASE, _GPIO_PINMASK_3 or _GPIO_PINMASK_4)
GPIO_Analog_Input(@GPIOA_BASE, _GPIO_PINMASK_0 or _GPIO_PINMASK_1 or _GPIO_PINMASK_2)
GPIO_Analog_Input(@GPIOA_BASE, _GPIO_PINMASK_3 or _GPIO_PINMASK_4 or _GPIO_PINMASK_5)
GPIO_Analog_Input(@GPIOA_BASE, _GPIO_PINMASK_6 or _GPIO_PINMASK_7)
'*******************************************************************************
'*******************************************************************************
rem Configure DMA Controller, Stream 0,Chanel 0 for ADC
rem Enable DMA2 CLOCK
RCC_AHB1ENR.DMA2EN=1
rem Disable the DMA Stream by resetting EN bit to be able to change bit registers
DMA2_S0CR = 0
rem wait until EN=0 to make sure DMA is stopped
while (DMA2_S0CR.EN=1) wend
rem All Stream Status dedicated registers to be cleared
DMA2_LIFCR.CTCIF0=1
rem Set peripheral port register address
DMA2_S0PAR = @ADC_CDR
rem Set memory address
DMA2_S0M0AR = @adcr
rem total number of data items ;
rem For 24 channels * 1 sample/channel
DMA2_S0NDTR = 24
rem Direct mode
DMA2_S0FCR.DMDIS=0
rem Select DMA2 channel request number (CH0)
DMA2_S0CR.CHSEL2=0
DMA2_S0CR.CHSEL1=0
DMA2_S0CR.CHSEL0=0
rem Config the stream priority (to Very High)
DMA2_S0CR.PL1=1
DMA2_S0CR.PL0=1
rem Memory data size to 32 bit
DMA2_S0CR.MSIZE1=1
DMA2_S0CR.MSIZE0=0
rem Peripheral data size to 32 bit
DMA2_S0CR.PSIZE1=1
DMA2_S0CR.PSIZE0=0
rem Memory increment mode
DMA2_S0CR.MINC = 1
rem Peripheral increment mode
DMA2_S0CR.PINC = 0
rem Burst mode PERIPHERAL
DMA2_S6CR.PBURST1=0
DMA2_S6CR.PBURST0=0
REM Burst mode Memory
DMA2_S0CR.MBURST1=0
DMA2_S0CR.MBURST0=0
rem Data transfer direction (peripheral to memory)
DMA2_S0CR.DIR1=0
DMA2_S0CR.DIR0=0
rem peripheral flow controller ,DMA flow
DMA2_S0CR.PFCTRL=0
rem Transfer complete interrupt enable
DMA2_S0CR.TCIE=1
rem Double buffer mode
DMA2_S0CR.DBM=0
rem Circular mode
DMA2_S0CR.CIRC=1
rem FIFO Mode ENABLE(DMDIS) ;TRESHOLD=FULL FIF0(11)
DMA2_S0FCR.DMDIS=1
DMA2_S0FCR.FTH1=1
DMA2_S0FCR.FTH0=1
rem Stream enable (start the DMA Stream0)
DMA2_S0CR.EN=1
'*******************************************************************************
'*******************************************************************************
rem ADC Common Data Register
REM Direct memory access mode for multi ADC mode; 01: DMA mode 1 enabled
ADC_CCR.DMA0=1
rem Multi ADC mode selection;Triple mode: ADC1,2 and 3 working together;Regular simultaneous mode
ADC_CCR.MULT4=1
ADC_CCR.MULT3=0
ADC_CCR.MULT2=1
ADC_CCR.MULT1=1
ADC_CCR.MULT0=0
rem Common ADC Register DMA disable selection DDS (for multi-ADC mode),bit13
ADC_CCR.B13=1
Rem ADC prescasler PCLK2 divided by 4 (01) ; PCLK2 divided by 2 (00)
ADC_CCR.17=0
ADC_CCR.16=0
'****************************************
rem ADC 1,2,3 Input configuration
rem Sample time is 28 Cycle for 1LSB accuracy (see Rain ecuation 1)!!
rem ADC1 :In0, In1, In2, In3, In4, In5, In6, In6
rem ADC2: In7, In10, In11, In12, In13, In14, In14, In14
rem ADC3 :In4, In5, In6, In7, In8, In9, In14, In15
ADC1_SMPR2=599186
ADC2_SMPR1=9362
ADC2_SMPR2=4194304
ADC3_SMPR1=73728
ADC3_SMPR2=306782208
rem Regular chanel sequence length (8)
ADC1_SQR1=7340032
ADC2_SQR1=7340032
ADC3_SQR1=7340032
rem Channel input sequence configuration register
ADC1_SQR2=198
ADC1_SQR3=172066848
ADC2_SQR2=462
ADC2_SQR3=483798343
ADC3_SQR2=494
ADC3_SQR3=310614180
'****************************************
rem Scan mode must be enabled when using more than 1 channel / ADC
ADC1_CR1.SCAN=1
ADC2_CR1.SCAN=1
ADC3_CR1.SCAN=1
'**********************************
rem Continuous conversion enabled for all 3 ADC's
ADC1_CR2.CONT = 1
ADC2_CR2.CONT = 1
ADC3_CR2.CONT = 1
'*******************************************************************************
rem ADC control register 2 (ADC_CR2), A/D Converter ON / OFF
ADC1_CR2.ADON = 1
ADC2_CR2.ADON = 1
ADC3_CR2.ADON = 1
'*******************************************************************************
EnableInterrupts()
NVIC_IntEnable(IVT_INT_DMA2_Stream0)
'*************************************************************************