I am using the code that came with an example, just changed it to run at 80MHz instead of 64MHz. XT with PLL is set in config bits.
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// (must be within 0.8 MHz to 8 MHz range)
// PLLPRE<4:0> = 0 -> N1 = 1 8MHz
CLKDIVbits.PLLPRE = 0; // 8mhz crystal, so no divisor
// multiply up the 8mhz (must be within 100 MHz to 200 MHz range)
PLLFBD = 18; // PLLDIV<8:0> = 18 -> M = 20 8MHz * 20 = 160MHz
// (must be within 12.5 MHz to 80 MHz range)
CLKDIVbits.PLLPOST = 0; // PLLPOST<1:0> = 0 -> N2 = 2 160MHz / 2 = 80MHz
Thanks,
Steve