When the device enters IDLE mode, the module can continue normal operation if the USIDL (UxMODE<13>) control bit is cleared. If USIDL=1, the module will stop and any transmission or reception in progress will be aborted.

At the end, a brief description of the registers of the UART module is presented

NAME	ADR	15	14	13	12	11	10	9
U1MODE	0x020C	UARTEN	-	USIDL	-	-	ALTIO	-
U1STA	0x020E	UTXISEL	-	-	-	UTXBRK	UTXEN	UTXBF
U1TXREG	0x0210	-	-	-	-	-	-	-
U1RXREG	0x0212	-	-	-	-	-	-	-
U1BRG	0x0214	Baud-rate generator prescale
U2MODE	0x0216	UARTEN	-	USIDL	-	-	ALTIO	-
U2STA	0x0218	UTXISEL	-	-	-	UTXBRK	UTXEN	UTXBF
U2TXREG	0x021A	-	-	-	-	-	-	-
U2RXREG	0x021C	-	-	-	-	-	-	-
U2BRG	0x021E	Baud-rate generator prescale

Table 10-2 Description of UART module registers

8	7	6	5	4	3	2	1	0	RESET STATE
-	WAKE	LPBACK	ABAUD	-	-	PDSEL<1:0>		STSEL	0x0000
TRMT	URXISEK<1:0>		ADDEN	RIDLE	PERR	FERR	OERR	URXDA	0X0000
UTX8	Transmit register								0x00uu
Transmit register									0x00uu
-	WAKE	LPBACK	ABAUD	-	-	PDSEL<1:0>		STSEL	0x0000
TRMT	URXISEK<1:0>		ADDEN	RIDLE	PERR	FERR	OERR	URXDA	0X0000
UTX8	Transmit register								0x00uu
Transmit register									0x00uu

Table 10-2 (continued)

UARTEN – UART enable bit (UARTEN=0 UART is disabled, UARTEN=1 UART is enabled)
USIDL – Stop in IDLE mode bit (UISDL=0 continue operation in IDLE mode, 
        USIDL=1 discontinue operation in IDLE mode)
ALTIO – UART alternate I/O selection bit (ALTIO=0 UART communicates using UxTX 
        and UxRX I/O pins, ALTIO=1 UART communicates using UxATX and UxARX I/O pins)
WAKE – Enable wake-up on START bit detect during SLEEP mode bit
LPBACK – UART loop back mode select bit
ABAUD – Auto baud enable bit
PDSEL<1:0> - Parity and data selection bits
      00 – 8-bit data, no parity
      01 – 8-bit data, even parity
      10 – 8-bit data, odd parity
      11 – 9-bit data, no parity
STSEL – STOP  selection bit (STSEL=0 one STOP bit, STSEL=1 two STOP bits)
UTXISEL – Transmission interrupt mode selection bit (UTXISEL=0 interrupt when a character is 
tranferred to the transmit shift register, UTXISEL=1 interrupt when a character is tranferred 
to the transmit shift register and the  transmit buffer becomes empty)

UTXBRK – Transmit break bit ( UTXBRK=0 UxTX pin operates normally, 
         UTXBRK=1 UxTX pin is driven low, regardless of transmitter state)
UTXEN – Transmit enable bit (UTXEN=0 UART transmitter disabled, 
        UTXEN=1 UART transmitter enabled)
UTXBF – Transmit buffer full status bit (UTXBF=0 transmit buffer is not full, 
        UTXBF=1 Transmit buffer is full)
TRMT – Transmit shift register is empty bit (TRMT=0 transmit shift register is not empty, 
transmission in progress, TRMT=1 transmit shift register is empty, transmission completed)

URXISEL<1:0> - Receive interrupt mode selection bits
        0x – interrupt flag bit is set when a charatcer is received
        10 - interrupt flag bit is set when receive buffer is ¾ full (3 locations full)
        11 - interrupt flag bit is set when receive buffer is full (all 4 locations full)
        
ADDEN – Address character detect 
(ADDEN=0 address detect mode disabled, ADDEN=1 address detect mode enabled)

RIDLE – Receiver IDLE bit 
(RIDLE=0 UxRSR not empty, data is being received, RIDLE=1 receiver is  IDLE)

PERR – Parity error status bit
FERR – Framing error status bit
OERR – Recive buffer overrun error status bit
URXDA – Receive buffer data available bit 
(URXDA=0 receive buffer is is empty, URXDA=1 receive buffer has data, 
at least one more character can be read)