When control bits OCM<2:0> are set to the values 110 or 111, the output compare module is configured for the pulse width modulation (PWM) mode. The PWM mode is available without fault protection input or with fault protection input. For the second PWM mode the OCxFA or OCxFB input pin is used. Fig. 6-8 shows an example of microcontroller dsPIC30F4013 connection to the inverter including the feedback error signal. The inverter controls the operation of motor M

6.3.1 PWM mode without fault protection input

When control bits OCM<2:0> are set to 110, the output compare module operates in this mode. In PWM mode the OCxR register is a read only slave duty cycle register. The OCxRS is a buffer register written by the user to update the PWM duty cycle.On every timer to period register match event (end of PWM period), the duty cycle register, OCxR, is loaded with the contents of OCxRS.The interrupt flag is asserted at the end of each PWM period. When configuring the output compare module for PWM mode of operation, the following steps should be taken:

1. Set the PWM period by writing to the selected timer period register, PRy.
2. Set the PWM duty cycle by writing to the OCxRS register.
3. Write the OCxR register with the initial duty cycle.
4. Enable interrupts for the selected timer.
5. Configure the output compare module for one of two PWM operation modes by writing 100 to control bits OCM<2:0> (OCxCON<2:0>).
6. Set the TMRy prescale value and enable the selected time base.

6.3.2 PWM mode with fault protection input pin

When the control bits OCM<2:0> areset to 111, the outpu compare module is configured for the PWMmode of operation. All functions derscribed in section 6.3.1 apply, with the addition that in this mode in addition to the output pin OCX the use is made of the signal from the input pin OCxFA for the output compare channels 1 to 4 or from the inpit pin OCxFB for the output compare channels 5 to 8. The signal at input pin OCxFA or OCxFB is a feedback error signal of the inverter related to a possible hazardous state of operation of the inverter. If the input pin OCxFA or OCxFB is low, the inverter is onsidered to be in a hazardous (error) state. Then the output OCx pin of the output compare module operating in the PWM mode is disabled automatically and the pin is driven to the high impedance state. The user may elect to provide a pull-down or pull-up resistor in order to define the state of OCx pin which is in thisstate disconnected from the rest of the output compare module. In the state of inverter fault, upon detection of the fault condition and disabling of pin OCx, the respective interrupt flag is asserted and in the register OCxCON the OCFLT bit (OCxCON<4>) is set. If enabled, an interrupt of the output compare module will be generated.