9.5.1 SPI module operation in SLEEP mode

When the device enters SLEEP mode, the system clock is disabled. If the SPI module is in master mode when the microcontroller enters SLEEP mode, the SPI clock is also disabled. If the SPIx module enters SLEEP mode in the middle of a transmission/reception, then the transmission/reception is aborted. Since there is no automatic way to prevent an entry into SLEEP mode, the user software must synchronize entry into SLEEP with SPI module operation. The transmitter or receiver does not continue with partially completed transmission at wake-up. Since the clock pulses at SCKx are externally provided for slave mode, the module will continue to function in SLEEP mode. It will complete any transaction during the transition into SLEEP. On completion of a transaction, the SPIRBF status flag for interrupt request of the SPI module is set. If the SPI interrupts are enabled (SPIxIE=1), the device will wake-up from SLEEP. If the SPI interrupt periority level is greater than the present CPU priority level, code execution will resume at the SPIx interrupt vector location. Otherwise, code execution will continue with the instruction that previously invoked SLEEP mode. Entering or waking-up from SLEEP mode does not influence the operation of the SPI module in slave mode nor does it change the contents of the SPI module registers.

9.5.2 SPI module operation in IDLE mode

When the device enters IDLE mode, the system clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) selects whether the module will stop or continue functioning on IDLE. If SPISID (SPIxSTAT<13>) bit is cleared, the SPI module will continue operation in IDLE mode. If SPISID (SPIxSTAT<13>) bit is set, the SPI module will stop communication on entreing IDLE mode. It will operate in the same manner as it does in SLEEP mode. Table 9-2 describes pins of the SPI module depending on the operational mode. At the end of this section a description of the UART registers for dsPIC30F is presented.

NAME	TYPE	DESCRIPTION
SCKx	Input / Output	SPI clock signal output or input
SDIx	Input	SPI data reception input pin
SDOx	Output	SPI data transmisson output pin SPI slave device selection control pin Write/Read enable pin in slave mode if the control bit SSEN (SPIxCOPN<7>) is set
SSx	Input / Output	Used as RAM synchronization pin when the control bits FRMEN and SPIFSD (SPIxCON<13:14>) are set to the value 10 or 11

Table 9-2 Description of SPI module pins A brief description follows of the SPI module registers of a dsPIC30F4013 device.

NAME	ADR	15	14	13	12-7	6	5	4	3	2	1	0	RESET STATE
SPI1STAT	0x0220	SPIEN	-	SPISIDL	-	SPIROV	-	-	-	-	SPITBF	SPIRBF	0x0000

Table 9-3 Status and control register SPI1STAT

SPIEN – SPI enable bit (SPIEN=0 disables module, SPIEN=1 enables module)
SPISIDL – Stop in IDLE mode bit (SPISIDL=0 continue operation, SPISIDL=1 discontinue operation)
SPIROV – Receive overflow flag bit
SPITBF – SPI transmit buffer full status bit (SPITBF=0 transmit started, SPIxTBF empty, 
         SPITBF=1 transmit not yet started, SPIxTBF is full)
SPIRBF – SPI receive buffer full status bit (SPIRBF=0 receive is not complete 
         SPIxRXB is empty, SPIRBF=1 receive complete SPIxRXB is full)

NAME	ADR	15	14	13	12	11	10	9	8	7	6	5
SPI1CON	0x0222	-	FRMEN	SPIFSD	-	DISSDO	MODE16	SMP	CKE	SSEN	CKP	MSTEN

Table 9-4a Control register SPI1CON

4	3	2	1	0	RESET STATE
SPRE<2:0>			PPRE<1:0>		0x0000

Table 9-4b continued

FRMEN – Framed SPI support bit
SPIFSD – Frame sync pulse direction control on SSx pin bit
(SPIFSD=0 frame sync pulse output (master), SPIFSD=1 frame sync pulse input (slave))
DISSDO – Disable SDOx pin bit
MODE16 – Word/byte communication select bit (MODE16=0 8-bit mode, MODE16=1 16-bit mode)
SMP – SPI data input sample phase bit (Master mode: SMP=0 input data sampled at middle of 
data output time, SMP=1 input data sampled at end of data output time; 
Slave mode: SMP must be cleared)

CKE – SPI clock edge select bit (CKE=0 serial output data changes on transition from 
IDLE clock state to active clock state, CKE=1 serial output data changes on transition from 
active clock state to IDLE clock state)

SSEN – Slave select enable bit 
(SSEN=0 SS1 pin not used by module, SSEN=1 SS1 pin used for slave mode)

CKP – Clock polarity select bit (CKO=0 IDLE state for clock is a low level, active state 
is a high level, CKO=1 IDLE state for clock is a high level, active state is a low level)

MSTEN – Master mode enable bit (MSTEN=0 slave mode, MSTEN=1 master mode)
SPRE<2:0> - Secondary prescale (master mode) bits
     000 – secondary prescale 8:1
     001 – secondary prescale 7:1
     ...
     110 – secondary prescale 2:1
     111 – secondary prescale 1:1
PPRE<1:9> - Primary prescale (master mode) bits
     00 – primary prescale 64:1
     01  - primary prescale 16:1
     10 – primary prescale 4:1
     11 – primary prescale 1:1

NAME	ADR	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	RESET STATE
SPI1BUF	0x0224	Transmit/Receive buffer (shared by SPI1TXB and SPI1RXB registers)																0x0000

Table 9-5 SPI1BUF register