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When control bits OCM<2:0> are set to 001, 010, or 011, the ouput compare module is set to the Single compare match mode. Now, the value loaded in the compare register OCxR is compared with time base counter TMR2 or TMR3. On a compare match event, depending on the value of OCM<2:0>, at the OCx output pin one of the following situations is possible:
program Output_Compare_test1; procedure Output1CompareInt; org $18;//OC1 address in the interrupt vector table begin IFS0.2 := 0; //Clear Interrupt Flag end; begin TRISD := 0; //OC1 (RD0) is output pin IPC0 := IPC0 or $0100; //Priority level of interrupt OC1IP<2:0>=1 IEC0 := IEC0 or $0004; //Output compare 1 enable interrupt OC1R := 10000; //OCR=TMR2 instant of level change at OC1 PR2 := $FFFF; //PR2 value maximal, time base 2 free-running T2CON := $8030; //Time base 2 operates using prescaler 1:256 and internal clock OC1CON := $0003; //Output compare 1 module configuration,TMR2 selected //Single compare mode, pin OC1 toggles while TRUE do //Endless loop nop; end.In the interrupt routine the request for the flag Output compare interrupt module is reset. At setting time base 2, preset register PR2 is set to the maximum value in orde to enable the free-running mode over the whole range, 0-65335. The value of OC1R defines the time of the change of state of pin OC1, i.e. of the duty cycle. The output compare module is configured to change the state of pin OC1 on single compare match with the value of OC1R.