The I2C module may be configured to operate in the following modes:

• I2C slave, 7-bit addressing,
• I2C slave, 10-bit addressing, and
• I2C master, 7- or 10-bit addressing.

A standard I2C interface makes use of two pins, SCL (clock line) and SDA (data line). The configuration of the I2C module is performed by using the following registers: I2CRV (8 bits), I2CTRN (8 bits), I2CBRG (9 bits), I2CON (16 bits), and I2CADD (10 bits). Functional block diagram of the I2C module is shown in Fig. 12-1. The I2CCON and I2CSTAT are 16-bit control and status registers, respectively. The content of the I2CCON control register may be read or written and so is the content of the 10 higher bits of the I2CSTAT status register. The lower 6 bits of the status register are read only. The I2CRSR shift register performs parallel-series conversion of data. Data to be transmitted are written in the I2CTRN buffer register, whereas received data are read from the I2CRCV buffer register. Address of a slave device on the I2C bus is written in the I2CADD register. The control bit A10M (I2CCON<10>) denotes whether the 7-bit or 10-bit addressing is used. Baud-rate is defined by the I2CBRG register, i.e. it holds the baud-rate generator reload value for the I2C module baud-rate generator.

12.1.1 I2C slave mode with 7-bit addressing

The 10-bit I2CADD register holds the slave device address. If the control bit A10M (I2CCON<10>) is cleared, address in the I2CADD is interpreted as a 7-bit address. When an address from a master device is received, only 7 lower bits are compared against the register I2CADD. If the control bit ADD10 (I2CCON<10>) is set, the value of the received address is compared in two cycles. At first, the 8 higher bits of the address are compared with the value '11110 A9 A8' (where A9 and A8 are two most significant bits of the device address held in the I2CADD register). If coincidence occurs, the lower 8 bits of the register I2CADD are compared with the 8 lower bits of the received address. The segments of an address usable in a standard I2C communication are specified by the standard I2C protocol. Table 12-1 shows the ranges of I2C addresses supported by the family of dsPIC30F devices together with the corresponding applications.

ADDRESS	DESCRIPTION
0x00	General call address or starting byte
0x01 – 0x03	Range of reserved addresses
0x04 – 0x77	Range of valid 7-bit addresses
0x78 – 0x7B	Range of valid 10-bit addresses
0x7C – 0x7F	Range of reserved addresses

Table 12-1 Standard I2C addresses supported by the family of dsPIC30F devices When in the slave mode, after setting the I2CEN (I2CCON<15>) enable bit, the slave function will begin to monitor the I2C bus to detect a START event. Upon deteting a START event, 8 bits are loaded to the I2CRSR shift register and the receved address is compared with the one from the I2CADD register. In the 7-bit address slave mode (A10M = 0) the bits I2CADD<6:0> are compared with the I2CRSR<7:1> bits. The bit I2CRSR<0> is ignored. The bits loaded to the shift register are sampled by the rising edge of SCL the clock. If an address match occurs, the slave sends an ACKNOWLEDGE of the 9-bit message, and an interrupt of the I2C module is generated (the flag SI2CIF is set) on the falling edge od the ninth bit (ACK – acknowledegement). The address detection is of no influence neither on the content of the receive buffer register I2CRCV nor on the value of the bit RBF (I2CSTAT<1>) which indicates that there is a new value in the receive buffer register. A typical standard I2C message consists of the START bit, address bits, R/W bit, acknowledge bit, data bits (eg. in an I2C communication with the EEPROM memory within data bits are the location address bits and the contents bits which are read out or written in), and STOP bit. A slave device transmit process is carried out as follows. Upon reception of the address part of the message containing the R/W bit, the device enters the transmit mode. It sends the ACKNOWLEDGE bit (ACK) and keeps the SCL clock signal low until the message byte is written to the transmit buffer I2CTRN. Then, the SCL clock signal is released, the bit SCLREL is set (I2CCON<12>), and the 8-bit message is sent from the I2CRSR shift register. The bits are sent on the falling edge of the SCL clock so that the SDA pin data are valid when the SCL closk is high. The interrupt request is generated on the falling edge of the ninth clock period irrespective of the status of the ACKLOWLEDGE (ACK) bit of the master device. The receive sequence of a slave device comprises the following steps. Upon receiving the address part of the message which contains the R/W bit cleared, the slave device is initiated for the receive mode. The incoming bits at the pin SDA are sampled on the rising edge of the SCL clock signal. After receiving 8 bits, if the receive buffer register I2CRCV is not full or the flag RBF (I2CSTAT<1>) is not cleared or the overflow status bit (I2COV (I2CSTAT<6>) of the receive buffer register I2CRCV is not set, the received bits contained by the shift register are transferred to the receive buffer register I2CRCV. Upon completion of the data transfer, the ACKNOWLEDGE bit ACK is generated as the ninth bit. If the flag RBF (I2CSTAT<1>) is set, the ACKNOWLEDGE bit ACK is not sent, but the interrupt request for the I2C is generated. In the case of the receive buffer overflow, the content of the shift register I2CRSR is not transferred to the receive buffer I2CRCV.

12.1.2 I2C slave mode with 10-bit addressing

The basic process of receiving and transmitting messages in the slave mode with 10-bit addressing is the same as in the slave mode with 7-bit addressing, the only difference is that the method of comparing addresses is much more complicated. The I2C standard specifies that after the START bit, any slave devise has to be addressed by two bytes. The control bit A10M (I2CCON<10>) is set meaning that a 10-bit address is in the I2CADD regsiter. After the START bit, the received data in the shift register I2CRSR<7:1> are compared with the expression '11110 A9 A8' containing two most significant bits of the device address, A9 and A8. If the result of the comparison is positive and the received R/W bit is cleared, an interrupt request is generated. At the same time the bit ADD10 (I2CSTAT<8>), which denotes partial match of the sent address and the slave address, is cleared. If the sent address and the slave address do not match or if the received R/W bit is set, the status bit ADD10 is cleared and the I2C is returned to the IDLE state. If there is partial match with the upper part of the address of the slave device, the lower part of the address is received and compared with the lower part of the address register I2CADD (I2CADD<7:0>). If a full match occurs, an interrupt request for the I2C module is generated and the status bit ADD10 (I2CSTAT<8>), indicating a full match of the 10-bit addresses, is set. If a full match does not occur, the status bit ADD (I2CSTAT<8>) is cleared and the module returns to the IDLE state. In the case when a full match of all 10 bits is detected, the master device may send the part of the message defining whether the slave is to receive data or trasmit data to the master. If the master repeats the START bit, the upper address bit is cleared and the R/W bit is set in order to avoid that the STOP bit is generated, and the master performs initialization of the slave device for the operation transmit data. The synchronization of the read and transmit data to the master is performed in the slave device by stretching the SCL clock signal. Whenever the slave device is to transmit data to the master, in both 7-bit or 10-bit addressing, stretching of the clock signal SCL is implemented by inserting the SCLREL (I2CCON<12>) bit on the falling edge of the ninth period of the clock. In the case when the transmit buffer is empty, the status bit TBF (I2CSTAT<0>) is cleared. Stretching of the SCL clock signal in the slave mode at data transmition is always performed irrespective of the state of the STREN (I2CON<6>) control bit which enables stretching of the SCL clock. This is not the case in the slave mode at data reception. The clock synchronization occurs after the ninth period of the SCL clock. Then, the slave device samples the value of the ACK acknowledgement bit (active low) and checks the value of the TBF status bit. If the ACK is low (the acknlowledge ACK bit active) and the TBF (I2CSTAT<0>) status bit is cleared, the SCLREL (I2CCON<12>) bit is cleared automatically. Setting the SCLREL (I2CCON<12>) bit low causes setting the external SCL line low. By the interrupt routine the user has to set the bit SCLREL (I2CCON<12>) before the slave device starts transmitting the message to the master. In this way the user is given the chance that in the interrupt routine writes data to be transferred to the I2CTRN transmit buffer register before the master device initiates a new transmit sequence. In essence, the STREN (I2CON<6>) control bit primarily serves for enabling stertching of the SCL clock signal during reception in the slave mode. When the STREN (I2CON<6>) bit is set, the pin of the SCL clock signal is kept low at the end of each receive sequence in the slave mode. Stretching of the clock signal is performed after the ninth period of the SCL clock signal during a receive sequence. On the falling edge of the ninth period of the SCL clock signal the value of the ACK ACKNOWLEDGE bit (active low) is sampled and the value of the TBF status bit is checked. If the ACK is low (bit ACK active) and the RBF (I2CSTAT<1>) status bit set, the SCLREL (I2CCON<12>) bit is cleared automatically. Setting the SCLREL (I2CCON<12>) bit low causes setting the external SCL line low. By the interrupt routine the user has to set the bit SCLREL (I2CCON<12>) before the slave device starts receiving data from the master. In this way the user is given the chance that in the interrupt routine reads out received data from the I2CRCV receive buffer before the master device initiates a new receive sequence. This prevents the overflow of the I2CRCV receive buffer register.

12.1.3 I2C master mode

A master device differs from a slave device in that it generates the system SCL serial clock, and START and STOP bits. Each data transfer is ended by a STOP bit or by the repeated START bit. A repeated START bit also means the beginning of a new data transfer, but the I2C bus is still busy by the current communication session. In the master mode serial data are transferred via the SDA pin in synchronism with the SCL clock signal. The firstbyte to be sent contains the 7-bit address of the slave (the device for whom the message is intended) and one bit for data direction R/W. In the case of data transmit the R/W bit is cleared (logic zero). The STARTand STOP bits are sent in order to recognize the beginning and end of a communication session, i.e. of a data transfer. In the master mode when receiving data, the 7-bit address of the slave (the device for whom the message is intended)and one bit for data direction R/W are sent first. In the case of data receive the R/W bit is set (logic one). Serial data are transmitted or received via pin SDA in synchronism with the SCL clock signal. Serial data are received 8 bits per cycle and each cycle is ended by sending the ACKNOWLEDGE ACK bit. The START and STOP bits are sent in order to recognize the beginning and end of a communication session. In the master mode the transmission of a 7-bit address or of the second part of a 10-bit address is performed by writing the desired value to the transmit buffer register I2CTRN. The user writes the desired value to the transmit buffer register only when the I2C module is in the WAIT state. By writing data to the transmit buffer register I2CTRN, the status flag TBF (I2CSTAT<0>) is set and the baud-rate generator is enabled to start counting and start data transmission. Each data bit or address bit from the shift register is sent to the SDA pin on the falling edge of the SCL clock signal. When the device is transmitting data, the transmit status flag TRSTAT (I2CSTAT<14>) is set. The reception in the master mode is enabled by setting, using the software, the RCEN (I2CCON<11>) control bit. In order to set the RCEN (I2CCON<11>) control bit, the I2C module has to be in the IDLE state. If this is not observed, the receive enable control bit RCEN (I2CCON<11>) will be ignored. The baud-rate generator starts counting and when it reaches the preset count it is reset, then the state of the SCL clock signal is changed, the ACKNOWLEGDE ACK bit is set, and the value of the SDA line is sampled on the rising edge of the clock signal and transferred to the shift register I2CRSR.