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5.1 External signal capture input mode

In the family of dsPIC30F microcontrollers the select by external input signal mode implies selecting the value from the TMR2 or TMR3 counter depending on the external input signal at pin ICx. The capture can be carried out depending on the external input signal:

  • on every falling edge of input signal applied at the ICx pin,
  • on every rising edge of input signal applied at the ICx pin,
  • on every risinig and every falling edge of input signal applied at the ICx pin,
  • on every fourth rising edge of input signal applied at the ICx pin,
  • on every 16th rising edge of input signal applied at the ICx pin,
The selection of the input captue mode is carried out by setting the control bits ICM<2:0> in the register ICxCON<2:0>. Also, by setting the control bits ICM<2:0> the reduction ratio in the prescaler 1, 4 , or 16 is set.
NOTE: The counter register of the input capture module is cleared upon RESET or switch off.

5.1.1 Simple capture mode

The simple capture mode, or the mode of simple capture, is the mode of the input capture module when the capture is done on every rising edge or every falling edge of the external input signal at the input pin ICx. In this mode the logic of the input capture module detects the change of the logical level at the input pin ICx, synchronizes the change with the phase of the internal clock, captures the value of the counter TMR2 or TMR3 and puts it into the FIFO buffer memory. The prescaler operates wth the ratio 1:1, i.e. without reduction. Since the input capture module comprises a four-level FIFO buffer, by setting the control bit ICI<1:0> (ICxCON<6:5>) it is possible to select the number of captures before an interrupt is generated. In this way capturing of fast external signals is made possible because while the counter values are captured and put into the FIFO buffer, it is possible to read previous values in the buffer and transfer them to the data memory. Selection of the counter of the timer module which is to be captured is done by setting the control bit ICTMR (ICxCON<7>). It is possible to select the 16-bit counters TMR2 (ICTMR=1) or TMR3 (ICTMR=0).

Example:

This example demostrates the operation of the input capture module in the simple capture mode. The value of the counter of timer2 TMR2 is captured on the falling edge of the IC1 signal (pin RD8). The captured value is put to portB. 
program Input_Capture_test;
procedure Input1CaptureInt; org $16;
begin
  LATB   := IC1BUF; //Read captured values and put to portB
  IFS0.1 := 0;      //Clear bit IC1IF (IFS<1>)
end;

begin
  TRISB  := 0;            //PORTB is output
  LATB   := 0;            //Initial value at PORTB
  TRISD  := $0100;        //Select pin IC1 (RD8) as input
  IPC0   := IPC0 or $0010; //Interrupt priority level IC1IP<2:0> = 1
  IEC0   := IEC0 or $0002; //Interrupt Input Compare module enable
  PR2    := $FFFF; //PR2 register at maximum, timer2 free-running
  T2CON  := $8030; //Timer 2 operates with prescaler 1:256 and internal clock
  IC1CON := $0082; //Configuration of Input  Capture module 1, selected TMR2,
                   //capture on falling edge
while TRUE do      //Endless loop
  nop;
end.
During interrupt routine clearing the interrupt Input Capture module request flag is mandatory and the captured value is read form the FIFO buffer. In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535. Input Capture module 1 is configured to capture values of timer 2 on falling edge of the signal at IC1 pin.

5.1.2 Prescaler capture mode

In this mode of operation of the input capture module the external signal is prescaled by the ratio 1:4 or 1:16 by setting the control bit ICM<2:0> to the values 100 or 101 respectively. In this way it is possible that the input capture module captures total value of the counter TMR2 or TMR3 for 4 or 16 periods of the external signal at the pin ICx. This is the way of measuring mean count rate by averaging 4 or 16 periods of an extarnal input signal. By setting the control bit IC1<1:0> (ICxCON<6:5>) it is also possible, like in the simple capture mode, to select the number of captures after which an interrupt request is generated. The selection of the timer module which is to be sampled is done by setting the control bit ICTMR (ICxCON<7>).
NOTE: If the time base is incremented by each instruction cycle, then the result of capturing will be available in the FIFO buffer one or two instruction cycles after the synchronous change at the input pin ICx, in phase with the internal clock of the microcontroller. An example of setting the captured value delayed by 1 or 2 instruction cycles TCY is shown in Fig. 5-2.
Attention! Before the operational mode is changed the input capture module should be turned off, i.e. the control bits ICM<2:0> cleared. If the mode is changed without clearing ICM<2:0>, there is a resudual content in the prescaler counter which leads to the premature sampling and interrupt request generation.

Example:

This example demonstrates the operation of the input capture module in the prescaler capture mode. The example shows capturing the values of the timer2 counter TMR2 on each fourth rising edge if the IC1 signal (pin RD8). The captured value is put to portB. 
program Input_Capture_test2;
procedure Input1CaptureInt; org $16;
begin
  LATB   := IC1BUF;  //Read captured value and put to PORTB
  IFS0.1 := 0;       //Clear IC1IF bit (IFS<1>)
end;

begin
  TRISB  := 0;            //PORTB iz output
  LATB   := 0;            //Initial value at PORTB
  TRISD  := $0100;        //Select pin IC1 (RD8) as input
  IPC0   := IPC0 or $0010; //Interrupt priority level is
  IEC0   := IEC0 or $0002; //Interrupt Input Capture module 1 enable
  PR2    := $FFFF;        //PR2 register at maximum, timer2 free-running
  T2CON  := $8030;        //Timer 2 operates with prescaler 1:256 and internal clock
  IC1CON := $0084;        //Configuration of Input  Capture module 1, selected TMR2,
                          //capture on each 4th rising edge
while TRUE do             //Endless loop
  nop;
end.
During interrupt routine clearing the interrupt Input Capture module request flag is mandatory and the captured value is read form the FIFO buffer. In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535. Input Compaer module 1 is configured to capture values of timer 2 on each fourth rising edge of the signal at IC1 pin.

5.1.3 Edge detection mode

Capturing the value of TMR2 or TMR3 counter can be done on every rising and every falling edge of the external input signal applied to the ICx pin. The edge detection mode is selected by setting the ICM<2:0> (ICxCON<2:0>) control bits to 001. In this mode the prescaler counter can not be used. The input capture module interrupt request is generated on every rising and every falling edge (ICxIF bit is set). It not possible to generate an interrupt request after 2, 3, or 4 captures by setting the control bits ICI<1:0> (ICxCON<6:5>) because in this mode they are ignored. Every capture event generates an interrupt. As a consequence no overflow of the FIFO buffer is possible.
NOTE: If the time base is incremented by each instruction cycle, then the result of capturing will be available in the FIFO buffer one or two instruction cycles after the synchronous change at the input pin ICx, in phase with the internal clock of the microcontroller. An example of setting the captured value delayed by 1 or 2 instruction cycles TCY is shown in Fig. 5-2.
pic-microcontrollers-programming-dspic-in-pascal-chapter-05-image-2
Fig. 5-2 An example of setting the captured value delayed by 1 or 2 instruction cycles TCY
Reading data from FIFO buffer – Each input capture module comprises a four-level (16-bit) FIFO buffer for accomodation of the captures. The access to the captures in the FIFO buffer is via the ICxBUF register. In addition, there are two status flags ICBNE (ICxCON<3>) and ICOV (ICxCON<4>) defining the status of the FIFO buffer. The ICBNE status flag denotes that the FIFO buffer is not empty. This flag is cleared by hardware when the last word is read from the FIFO buffer or during the reset of the input capture module by setting the control bits ICM<2:0> to value 000. ICBNE is also reset during RESET. The other status flag ICOV denotes the state of overflow of the FIFO buffer, i.e. when after four captures which have not been transferred to the data memory the fifith capture is being put in. No interrupt request is generated then, the ICOV bit is set and the values of the five captures and all subsequent captures are ignored. Clearing of this bit is done by hardware upon reading of all four captures from the FIFO buffer, or by resetting of the input capture module. Also, the microcontroller RESET clears this flag.