6.2 Dual compare match mode
When control bits OCM<2:0> are set to 100 or 101, the output compare module is cobfigured for the dual compare match mode. In this mode the module uses two registers, OCxR and OCxRS, for the compare match events.
The values of both registers are compared with the time base counter TMR2 or TMR3. On a compare match event of the OCxR register and register TMR2 or TMR3 (selectable by control bit OCTSEL), the leading edge of the pulse is generated at the OCx pin; the register OCxRS is then compared with the same time base register and on a compare match evenet, the trailing edge at the OCx pin is generated.
Depending on the value of control bit OCM<2:0> at the output pin OCx is generated:
- single pulse and an interrupt request,
- a sequence of pulses and an interrupt request.
6.2.1 Dual compare match mode, single output pulse at pin OCx
When control bits OCM<2:0> are set to 100, the output compare module is configured for the dual compare match (OCxR and OCxRS registers), single output pulse mode. By setting the control bits OCTSEL the time base counter for comparison is selected. v. Two instruction clocks after pin OCx is driven low, an interrupt request OCxIF for the output compare module is generated. Pin OCx will remain low until a mode change has been made or the module is disabled. If the contents of time base register PRy<OCxRS, no trailing edge and the interrupt request are generated and if PRy<OCxR no leading edge is generated at pin OCx. Fig. 6-6 shows timing diagram of the operation of the output compare module in the dual compare match mode, single pulse at the output pin OCx (OCxR < OCxRS < PRy).
Fig. 6-6 Timing diagram of the operation of the output compare module in the dual compare match mode, single pulse at the output pin OCx
6.2.2 Dual compare match mode, sequence of output pulses at pin OCx
When control bits OCM<2:0> are set to 101 the output compare module is configured for the dual compare match (OCxR and OCxRS registers), a sequence of output pulses is generated at the output OCx pin. After a compare match occurs between the compare time base (TMR2 or TMR3) and OCxR registers, the output pin OCx is driven high, i.e. the leading edge is generated at pin OCx. When a compare match occurs between the time base (TMR2 or TMR3) and OCxRS registers, the trailing edge at pin OCx is generated, i.e. pin OCx is driven low. Two instruction clocks after, an interrupt request for the otput compare module is generated. In this mode
it is not necessary to reset the ouput compare module in order that the module could react on equalization of the TRy and OCxR or OCxRS registers. Even if the interrupt of the output compare module is enabled (OCxIE is set), it is required that in
the interrupt routine the interrupt request flag of the output compare module OCxIF is reset.
If the preset register PRy < OCxRS, the trailing edge at pin OCx will not be generated. Fig. 6-7 shows an example of operation of the output compare module in the dual compare match mode, a sequence of output pulses at the output pin OCx (OCxR < OCxRS < PRy).
Fig. 6-7 Timing diagram of the operation in the dual compare match mode, pulse sequence at the output pin OCx
Example:
The output compare module compares the value of registers OC1R and OC1RS with the value of the counter TMR2 of the time base 2 and on compare match event toggles the logical level at pin OC1.
program Output_compare_test2;
procedure Output1CompareInt; org $18;//Address of OC1 in the interrupt table
begin
IFS0 :=0; //Reseting of interrupt OC1 module flag
end;
begin
TRISD := IPC0 or $0100; //OC1 (RD0) is output
IPC0 := IEC0 or $0004; //Output Compare module 1 interrupt enable
OC1R := 30000; //If OC1R=TMR2, leading edge at pin OC1
OC1RS := 100; //If OC1RS=TMR2, trailing edge at OC1
PR2 := $FFFF; //PR2 at maximum, time base 2 free-running
T2CON := $8030; //Time base 2 operates with prescaler 1:256 and internal clock
OC1CON := $0005; //Configuration of Output Compare 1 module,
//TMR2 selected, dual compare match, pulse sequence
while TRUE do // Endless loop
nop;
end.
In the interrupt routine
the interrupt request flag of the Output Compare module is reset. In presetting timer 2, register PR2 is set to the maximum value in order to enable free-running mode of the timer within the entire range of values 0 to 65535. The value of OC1R defines the instant of the leading edge at pin OC1, the value of OC1RS defines the instant of the trailing edge. The Otput Compare module is configured to toggle continually the logical level at pin OC1 on dual compare match event with the values of registers OC1R and OC1RS.
