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When control bits OCM<2:0> are set to 100 or 101, the output compare module is cobfigured for the dual compare match mode. In this mode the module uses two registers, OCxR and OCxRS, for the compare match events.The values of both registers are compared with the time base counter TMR2 or TMR3. On a compare match event of the OCxR register and register TMR2 or TMR3 (selectable by control bit OCTSEL), the leading edge of the pulse is generated at the OCx pin; the register OCxRS is then compared with the same time base register and on a compare match evenet, the trailing edge at the OCx pin is generated. Depending on the value of control bit OCM<2:0> at the output pin OCx is generated:
program Output_compare_test2; procedure Output1CompareInt; org $18;//Address of OC1 in the interrupt table begin IFS0 :=0; //Reseting of interrupt OC1 module flag end; begin TRISD := IPC0 or $0100; //OC1 (RD0) is output IPC0 := IEC0 or $0004; //Output Compare module 1 interrupt enable OC1R := 30000; //If OC1R=TMR2, leading edge at pin OC1 OC1RS := 100; //If OC1RS=TMR2, trailing edge at OC1 PR2 := $FFFF; //PR2 at maximum, time base 2 free-running T2CON := $8030; //Time base 2 operates with prescaler 1:256 and internal clock OC1CON := $0005; //Configuration of Output Compare 1 module, //TMR2 selected, dual compare match, pulse sequence while TRUE do // Endless loop nop; end.In the interrupt routine the interrupt request flag of the Output Compare module is reset. In presetting timer 2, register PR2 is set to the maximum value in order to enable free-running mode of the timer within the entire range of values 0 to 65535. The value of OC1R defines the instant of the leading edge at pin OC1, the value of OC1RS defines the instant of the trailing edge. The Otput Compare module is configured to toggle continually the logical level at pin OC1 on dual compare match event with the values of registers OC1R and OC1RS.