In the master mode of the I2C module the value of the baud rate is defined by the preset value of the baud-rate counter BRG in the I2CBRG register. The baud-rate counter counts down from the preset value to zero. When zero is reached, the preset value BRG is written to the counter again. In the case when the clock arbitration occurs, writing the preset value BRG to the baud-rate counter is performed when the pin SCL is high.
According to the I2C standard, the frequency of the clock signal FSCK is 100kHz or 400kHz. The user has the optionofspecifying the baud rate up to 1MHz. The following expression defines in the I2CBRG register the value of the desired baud rate:
The arbitration of the clock signal is performed each time when the master device releases the SCL pin (the SCL pin is set high) during reception, transmission, or the repeated START state or STOP state. When the master device releases the SCL pin, the baud-rate generator does not operate. The preset value BRG is written each time the SCL pin is set high while the baud-rate generator does not operate. Then, the baud-rate counter starts counting and generates the SCL clock signal.