The UART transmitter block diagram is shown in Fig. 10-2. The heart of the transmitter is the transmit shift register UxTSR where parallel data (9-bit word) are converted to serial data sequences. The shift register obtains its data from the transmit FIFO buffer, TxTXREG. The write-only UxTXREG register is loaded with data by the user software. The UxTXREG is not loaded until the STOP bit has been transmitted from the previous load. As soos as the STOP bit is transmitted, the UxTSR is loaded with new data from the UxTXREG register (if available).
Fig. 10-2 UART transmitter functional block diagram