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In the master mode, the clock provided to the SPI module is the instruction cycle TCY . This clock will then be prescaled by the primary prescaler, specified by PPRE<1:0> (SPIxCON<1:0>), and the secondary prescaler, specified by SPRE<2:0> (SPIxCON<4:2>). The prescaled instruction clock becomes the serial clock and is provided to external devices via the SCKx pin.
Attention!!! Note that the SCKx signal clock is not free running for normal SPI modes (8-bit or 16-bit). It will only run for 8 or 16 pulses when the SPIxBUF is loaded with data. It will however, be continuous for framed modes.The SCKx clock frequency as a function of the primary and secondary prescaler settings is calculated by the following equation
|FCY = 30 MHZ||SECONDARY PRESCALER SETTINGS|
|Primary prescaler settings|
|1:1||30 000||15 000||7 500||5 000||3 750|
|4:1||7 500||3 750||1 875||1 250||938|
|Fcy = 5 Mhz|
|Primary prescaler settings|
|1:1||5 000||2 500||1 250||833||625|
NOTE: SCKx clock frequencies shown in kHz. All frequencies are not supported; electrical characteristics of individual microcontrollers of dsPIC30F family should be consulted.
program SPITest const CS_PIN = 0 ' DAC CS pin dim value as word sub procedure InitMain() TRISF.CS_PIN = 0 ' CS pin LATF.CS_PIN = 1 ' Set CS to inactive Spi1_Init_Advanced(_SPI_MASTER, _SPI_16_BIT, _SPI_PRESCALE_SEC_1, _SPI_PRESCALE_PRI_1, _SPI_SS_DISABLE, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_HIGH, _SPI_ACTIVE_2_IDLE) ' Init SPI end sub ' DAC increments (0..4095) --> output voltage (0..Vref) sub procedure DAC_Output(dim valueDAC as word) while (SPI1STAT.1 = 1) ' wait for SPI module to finish, if doing something nop wend LATF.CS_PIN = 0 ' CS enable for DAC SPI1BUF = 0x3000 or valueDAC ' Write CurrentValue to DAC (0x3 is required by DAC) while (SPI1STAT.1 = 1) ' Wait for SPI module to finish write nop wend LATF.CS_PIN = 1 ' CS disable for DAC end sub main: InitMain() while true value = 1 while value < \$FFF DAC_Output(value) Delay_ms(5) value = value+1 wend wend end.Procedure Spi2_Init initializes the SPI module in master mode 8-bit formatted, without the SS2 pin, sampling in the middle of the SPI cycle, prescale 1:8, and the clock FCY:1 low while waiting. If another format or communication speed is desired, the procedure Spi2_Init_Advanced instead of Spi2_Init should be used. The procedure Spi2_Data_Ready reads the value of the status bit SPIRBF (SPI2STAT<0>) and checks if there are data loaded into the receive buffer register. The procedure Spi2_Write transmits data via the SPI module. Data reception is performed by the procedure Spi2_Read. The SPI moduled is disabled by the procedure Spi2_Stop (clearing the control bit SPIEN), and the SPI module enable (setting the control bit SPIEN) is performed automatically by the procedure Spi2_Init or Spi2_Init_Advanced.