6.1 Single compare match mode
When control bits OCM<2:0> are set to 001, 010, or 011, the ouput compare module is set to the Single compare match mode. Now, the value loaded in the compare register OCxR is compared with time base counter TMR2 or TMR3. On a compare match event, depending on the value of OCM<2:0>, at the OCx output pin one of the following situations is possible:
- OCx pin is high, initial state is low, and interrupt is generated,
- OCx pin is low, initial state is high, and interrupt is generated,
- State of OCx pin toggles and interrupt is generated.
6.1.1 Single compare match, pin OCx driven high
In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 001. Also, the time base counter (TMR2 or TMR3) should be selected. Initially, output pin OCx is set low and will stay low until a match event occurs between the TMRy and OCxR registers. One instruction clock after the compare match event, OCx pin is driven high and will remain high until a change of the mode or the module is disabled. TMRy goes on counting. Twop instruction clocks after OCx pin is driven high, the interrupt, OCxIF flag, is generated. Timing diagram of the single compare mode, set OCx high on compare match event is shown in Fig. 6-2.
Fig. 6-2 Timing diagram of the single compare mode, set OCx high on compare match event
6.1.2 Single compare match, pin OCx driven low
In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 010. Also, the time base counter (TMR2 or TMR3) should be enabled. Initially, output pin OCx is set high and it stays high until a match event occurs between the TMRy and OCxR registers. One instruction clock after the compare match event OCx pin is driven low and will remain low until a change of the mode or the module is disabled. TMRy goes on counting. Two instruction clocks after OCx pin is driven low, the interrupt flag, OCxIF, is generated. Timing diagram of the single compare mode, set OCx low on compare match event is shown in Fig. 6-3.
Fig. 6-3 Timing diagram of the single compare mode,set OCx low on compare match event
6.1.3 Single compare match, pin OCx toggles
In order to configure the output compare module for this mode, control bits OCM<2:0> areset to 011. Also, the time base counter (TMR2 or TMR3) should be enabled. Initially, output pin OCx is set low and then toggles on each subsequent match event between the TMRy and OCxR registers. OCX pin is toggled one instruction clock the compare match event. TMRy goes on counting. Two instruction clocksafter the OCX pin is togglrd, the interrupt flag, OCxF, is generated. Figs. 6-4 and 6-5 show the timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy (PR2 or PR3)>OCxR (Fig. 6-4) or timer register PRy (PR2 or PR3)=OCxR (Fig. 6-5).
Fig. 6-4 Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy>OCxR
Fig. 6-5 Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy=OCxR
NOTE: OCx pin is set low on a device RESET. In the single compare mode, toggle output on compare match event the operational OCx pin state can be set by the user software.
Example:
Output compare module 1 is in the single compare mode: toggle current output of pin OC1. The output compare module compares the values of OC1R and TMR2 registers; on equality, the output of OC1 pin is toggled
program Output_Compare_test1
sub procedure Output1CompareInt org $18 'OC1 address in the interrupt vector table
IFS0.2 = 0 'Clear Interrupt Flag
end sub
main:
TRISD = 0 'OC1 (RD0) is output pin
IPC0 = IPC0 or $0100 'Priority level of interrupt OC1IP<2:0>=1
IEC0 = IEC0 or $0004 'Output compare 1 enable interrupt
OC1R = 10000 'OCR=TMR2 instant of level change at OC1
PR2 = $FFFF 'PR2 value maximal, time base 2 free-running
T2CON = $8030 'Time base 2 operates using prescaler 1:256 and internal clock
OC1CON = $0003 'Output compare 1 module configuration,TMR2 selected
'Single compare mode, pin OC1 toggles
while TRUE 'Endless loop
nop
wend
end.
In the interrupt routine the request for the flag Output compare interrupt module is reset. At setting time base 2, preset register PR2 is set to the maximum value in orde to enable the free-running mode over the whole range, 0-65335. The value of OC1R defines the time of the change of state of pin OC1, i.e. of the duty cycle. The output compare module is configured to change the state of pin OC1 on single compare match with the value of OC1R.