Digital signal processing (DSP) module is a part of the device specialized for fast execution of the basic mathematical operations (addition, subtraction and multiplication) and for performing automatically accumulation, logical shifting, rounding off and saturation. This module makes the dsPIC30F devices very powerful and considerably extends the scope of their applications.

Processing of digital signals is very demanding. One of the biggest problems is the multiplication required for processing of digital signals. The family of dsPIC30F devices has a hardware implemented multiplier which accelerates considerably the processing. The major part of digital signal processing reduces to calculating the sums of products of two arrays. This module has been designed to allow a fast calculation of the sum of products: Block diagram of the DSP module is shown in Fig.11-1. Fig. 11-1 illustrates the realization of the DSP module. In order to calculate the sum of products as fast as possible, the following additions have been made:

1. One data bus for reading the operands (array elements). This gives two data buses, X and Y. The advantage of this approach is that two samples can simultaneously appear at the input of the DSP module, be multiplied and the product added to the partial sum already existing in the accumulator.
2. A very fast hardware multiplier. The multipliers owing to their high complexities and voluminosities are difficult to be built-in in the majority of micoprocessors or microcontrollers. For this reason a multiplier is a part of the micoprocessor or microcontroller only in the applications when it is absolutely necessary, such as digital signal processing. The result of multiplication is a 32-bit quantity.
3. High precision is the property of the DSP module in order to achieve sufficiently good precision while calculating the sum of products of a large number of array elements. Even though 32 bits are sufficient for saving the product of two 16-bit values, 8 bits have been added to increase the precision. This means that the accumulator contains 40-bit data.
4. A barrel shifter serving for automatic hardware shifting of the values from the multiplier, accumulator, or data bus. This eliminates the need for any code for shifting (or multiply/divide by 2n ) of any value, thus the processing is accelerated.
5. An adder independent of the multiplier and other parts of the DSP module, which allows a parallel execution of several DSP instructions. E. g. two array members have been multiplied and should be added to the accumulator. While the adder performs adding the value from the multiplier to the value in the accumulator, the multiplier processes next two array elements. This logic allows that processing of one partial sum of products is carried out in one instruction cycle, i.e. pipelining.
6. Hardware rounding off, which is necessary at the end of the calculation of the sum of products, because the intermediate results are kept with a precision which is higher than required in order to reduce the error of the calculation. The rounding off can be convergent or conventional (non-convergent). This part of the DSP module further reduces the length of the corresponding code.
7. Hardware saturation logic which may, but need not, be enabled. This logic prevents the unwanted events at overflow. Namely, 40 bits may sometimes be insufficient, particularly if the summing is performed for two long arrays consisting of the elements having high numerical values. Enabling this logic is recommended since it mitigates the effects of the errors and unwanted phenomena while calculating the sum of products of two large arrays.