The described type B and C timers, as already mentioned, could be concatenated to form a 32-bit timer. Functional block diagram of the concatenated 32-bit timer is shown in Fig. 4-8.
Fig. 4-8 Type C timer functional block diagram (timer 3 module)
program TestTimer23 sub procedure Timer23Int org $22 ' Address in the interrupt vector table of timer3 LATD = not PORTD ' Invert port D IFS0 = 0 ' Clear interrupt request end sub main: TRISD = 0 ' Port D is output LATD = $AAAA ' Initial value at port D is set IPC1 = IPC1 or $1000 ' Timer3 priority is 1 IEC0 = IEC0 or $0080 ' Timer3 interrupt enabled PR2 = 34464 ' Interrupt period is 100 000 clocks PR3 = $0001 ' Total PR3/2=1*65536 + 34464 T2CON = $8038 ' Timer2/3 is enabled, internal clock is divided by 256 while TRUE ' Endless loop nop wend end.How does one set timer2/3 module to the 32-bit timer mode? The corresponding iterrupt bits, i.e. interrupt priority T3IPC=1, interrupt request bit T3IF=0, and interrupt enable bit T3IE=1 are set first (in the concatenated timer2/3 module interrupts are controlled by the control bits of the timer3 module and the operation of the timer2/3 module is controlled by the control bits of the timer2 module). Then the operation of the timer is activated TON=1, 32-bit operation is selected T32=1, and in this case the prescaler is configured for 1:256 ratio TCKPS<1:0>=11. The preiod register PR2/3 contains the value 100 000 distributed according to the formula PR3/2=PR3*65536 + PR2, PR3=1 and PR2=34464. How does one calculate the period of interrupt calls? Let the internal clock be adjusted to 10MHz. The corrsponding period is 100ns. Since the clock is divided by 256 (the prescaler reduces the clock 1:256) to form the clock of the timer, it follows that 100ns*256 = 25600ns, i.e. 25.6µs. At each 100 000 clocks an interrupt is called, i.e at each 2.56s or approximately once every two seconds. T = 100 000*25.6µs = 2.56s.
program TesTimer23 sub procedure Timer23Int org $22 'Address in the interrupt vector table of timer3 Inc(LATD) ' Increments the value of PORTD IFS0 = 0 ' Clear interrupt request end sub main: TRISD = 0 'PORTD is output TRISC = $2000 'PORTC<13>=1 T2CK is input pin LATD = $0 'Initial value at PORTL is set IPC1 = IPC1 or $1000 'Interrupt priority of timer3 is 1 IEC0 = IEC0 or $0080 'Interrupt of timer3 enabled PR2 = 10 'Interrupt peiod is 10 clocks PR3 = 0 'Total PR3/2=0*65536 + 10 T2CON = $800A 'Timer2/3 is synchronous counter of external pulses while TRUE 'Endless loop nop wend end.How does one set timer 2/3 module to the synchronous counter mode? Prescaler 1:1 is selected, external clock is enabled TCS=1, 32-bit operation is enabled T32=1, the operation of the timer1 module is enabled TON=1 in the control register T2CON (in 32-bit operation the control bits T3CON are ignored), interrupt bits of timer2/3 module are set (in the concatenated timer2/3 interrupts are controlled by the control bits of timer3 module), priority of interrupts T3IPC=1, interrupt request bit T3IF=0, and interrupt enable bit T3IE=1.
program TestTimer23 sub procedure Timer2Int org $20 'Address in the interrupt vector table of timer2 LATD = TMR2 'Signal length is displayed at port D IFS0.6 =0 'Interrupt request cleared end sub main: T2CON = 0 'Stops the Timer2 and reset control register TMR2 = 0 'Clear contents of the timer register PR2 = $FFFF 'Load the Period register with $FFFF IFS0.6 = 0 'Interrupt request cleared T2CON.6 = 1 'Set up Timer2 for Gated time accumulation mode T2CON.15 = 1 'Start Timer2 TRISD = 0 'PORTD is output TRISC = $2000 'PORTC<13>=1 is input pin IEC0.6 = 1 'Timer2 interrupt enable while TRUE 'Endless loop nop wend end.Why the period registers PR2 and PR3 are set to the maximum value and how does one measure even longer pulses? The main reason is to measure as long pulses as possible, i.e. the interrupt does not occur because the concatenated registers TMR3/TMR2 and PR3/PR2 are equal but, if possible, it is the ceonsequence of the falling edge of the GATE signal. Measuring even longer pulses can be accomplushed by setting the prescaler to higher reduction ratios 1:8, 1:64, or 1:256. In this way the range of measurement is extended but the accuracy is reduced.
NOTE: The timer modules 2 and 3 could operate independently as 16-bit timers. They coud be configured to operate in the following modes: 16-bit timer, 16-bit synchronous counter, and 16-bit gated time accumulation. The timer modules 2 and 3 can not operate as 16-bit asynchronous counters nor as real time clock sources (RTC).As a clock source, the timer2 and 3 modules use an external clock source or the internal clock FOSC/4 with the option of selecting the prescaler reduction ratio 1:1, 1:8, 1:64, or 1:256. The selection of the reduction ratio is achieved by the control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). When the timer2 and 3 modules form the concatenated 32-bit timer module, then the prescaler reduction ratio is selected by the timer2 module and the corresponding control bits of the timer3 module are ignored. The prescaler counter is reset only if: writing in the registers TMR2 or TMR3, writing in the registers PR2 or PR3, or the microcontroller is reset. It is important to note that the prescaler counter can not be reset when the timer1 module is disabled (TON=0) since the clock of the prescaler counter is stoped. Also, writing in T2CON/T3CON does not change the contents of TMR2/TMR3. In SLEEP mode the timer2 and 3 modules are not functional since the system clock is disabled. In IDLE mode the timer2 and 3 modules will continue operation if TSIDL bit is cleared. If this bit is set, the timer2 and 3 modules will stop until the microcontroller is waken up from IDLE mode. The characteristics of the timer4 and 5 modules are very similar to those of the timer2 and 3 modules. If concatenated to form a 32-bit timer, they could operate in the same modes as the timer2 and 3 modules. The only difference is that the timer4 and 5 modules are not used by other peripherals Iput capture and Output compare like the timer2 and 3 modules. Also, the timer5 module has no ability like the timer3 module to trigger an A/D conversion.
|TMR3HLD||0x0108||Timer3 holding register (32-bit operation only)||0x0000|
|PR2||0x010C||Period register 2||0xFFFF|
|PR3||0x010E||Period register 3||0xFFFF|
TON – Timer on control bit (TON=1 starts the timer, TON=0 stops the timer) TSIDL – Stop in IDLE mode bit (TSIDL=1 discontinue timer operation when device enters IDLE mode, TSIDL=0 continue timer operation in IDLE mode) TGATE – Timer gated time accumulation enable bit (TCS must be set to 0 when TGATE=1) TCKPS<1:0> - Timer input clock prescale select bits 00 – 1:1 prescale valu 01 – 1:8 prescale value 10 – 1:64 precale value 11 – 1:256 prescale value T32 – Timer 32-bit mode of timer4 and 5 select bit (T32=1 32-bit mode selected, T32=0 timer2 and 3 modules operate in 16-bit mode) TCS – Timer clock source select bit (TCS=1 external clock from pin T1CK, TCS=0 internal clock FOSC/4)