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The PWM period, specified by the value in the PRy register of the selected timer y, is calculated by:
TPWM=(PRy +1)TCY(TMRy prescale value),
and the PWM frequencyby:
Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz. The instruction clock frequency is FCY=FOSC/4, i.e. 10MHz. Timer 2 prescale setting is 4. Calculate the PWM period for the maximum value PR2=0xFFFF=65535.
TPWM = (65535+1) x 0.1µs x (4) = 26.21 ms, i.e. fPWM = 1/TPWM = 38.14 Hz.
6.4.2 PWM duty cycle
The PWM duty cycle is specified by the value written to the register OCxRS. It can be written to at any time within the PWM cycle, but the duty cycle value is latched into OCxR when the PWM period is completed. OCxR is a read only register. This provides a double buffering for the PWM duty cycle.
If the duty cycle register,OCxR, is loaded with 0000, the duty cycle is zero and pin OCx will remain low throughout the PWM period.
If the duty cycle register is greater that PRy, the output pin OCx will remain high throughout the PWM period (100% duty cycle).
If OCxR is equal to PRy, the OCx pin will be high in the first PWM cycle and low in the subsequent PWM cycle.
NOTE: In order to achieve as fine as possible control of PWM, it is necessary to enable as high as possible duty cycle adjustment. This is accomplished by adjusting the prescale value, clock value, and PWM frequency to achieve the highest possible value of PRy thus achieving the highest number of adjustment levels, i.e. the highest resolution.
6.4.3 Maximum resolution
The maximum resolution is calculated by the following formula:
Max PWM resolution [bits] = (log10TPWM - log(TCY x prescale value TMRy)) / log102
Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz. The instruction clock frequency is FCY=FOSC/4, i.e. 10MHz. Timer 2 prescale setting is 4. Calculate the maximum resolution for PWM frequency 48Hz.
Max PWM resolution [bits] = (log10(1/48) – log10(0.1µs x 4)) / log102 = 15.66 bits.
For this value of the PWM period and other selected parameters (prescale value, clock) it turns out that the PWM mode operates with almost maximum resolution.
Fig. 6-9 Timing diagram of the PWM mode of the output compare module