12.7.1 Operation of I2C module in SLEEP state

When the microcontroller enters SLEEP state, all clock sources are off, consequently the baud-rate generator stops operating and stays low (logic zero). If entering the SLEEP state occurs during transmission of a message, the current transmission is interrupted and the transmitted data are lost. Similarly, if entering the SLEEP state occurs during reception of a message, the current reception is interrupted and the received psrt of the message is lost.

12.7.2 Operation of I2C module in IDLE state

In the IDLE state the I2C module may continue operating if the control bit I2CSIDL (I2CCON<13>) is not set. If the bit I2CSIDL (I2CCON<13>) is set, the I2C module behaves like in the SLEEP state. Example: This example shows how to use the specialized I2C library of the mikroC compiler for dsPIC microcontrollers which allows easy initialization of the I2C module, writing, and reading data from the transmit and receive buffers of the I2C module, respectively. Specifically, the example shows the method of connecting the I2C module to the serial I2C EEPROM memory 24C02.

unsigned dAddr;

void main() {
 ADPCFG = 0xFFFF;
 PORTB = 0;
 TRISB = 0;
 
 dAddr = 0x02;

 I2c_Init(100000);
 I2c_Start(); // issue I2C start signal
 I2c_Write(0xA2); // send byte via I2C (command to 24cO2)
 I2c_Write(dAddr); // send byte (address of EEPROM location)
 I2c_Write(0xF4); // send data (data to be written)
 I2c_Stop();

 Delay_100ms();

 I2c_Start(); // issue I2C start signal
 I2c_Write(0xA2); // send byte via I2C (device address + W)
 I2c_Write(0x02); // send byte (data address)
 I2c_Restart(); // issue I2C signal repeated start
 I2c_Write(0xA3); // send byte (device address + R)
 PORTB = I2c_Read(1); // Read the data (NO acknowledge)
 I2c_Stop();

}//~!

The function I2C_Init initializes the I2C module, i.e. baud-rate. The function I2C_Start sets the conditions for START of the communication session on the I2C bus (defines the beginning of the message). The functions I2C_Write and I2C_Read enable that a microcontroller of the family dsPIC30F as a master can write or read from a peripheral having the I2C interface. In addition to these functions, also significant is the function I2C_Stop setting the state at the end of the I2C communication session (defines the end of the message). The I2C library of the mikroC compiler for dsPIC microcontrollers contains also the functions I2C_Repeated_Start and I2C_Is_Idle generating the state of a repeated start and the state of waiting of the I2C module, respectively. Fig. 12-2 shows the connection of a microcontroller of the family dsPIC30F to a serial I2C EEPROM memory 24C02. Finally, a description of the I2C module registers of the dsPIC30F4013 device is presented.

NAME	ADR	15	14	13	12	11	10	9
I2CRCV	0x0200	-	-	-	-	-	-	-
I2CTRN	0x0202	-	-	-	-	-	-	-
I2CBRG	0x0204	-	-	-	-	-	-	-
I2CCON	0x0206	I2CEN	-	I2CSIDL	SCLREL	IPMIEN	A10M	DISSLW
I2CSTAT	0x0208	ACKSTAT	TRSTAT	-	-	-	-	GCSTAT

Table 12-2 Description of I2C registers

8	7	6	5	4	3	2	1	0	RESET STATE
-	Receive buffer register								0x0000
-	Transmit buffer register								0x00FF
Baud-rate generator preset register									0x0000
SMEN	GCEN	STREN	ACKDT	ACKEN	RCEN	PEN	RSEN	SEN	0x0000
ADD10	IWCOL	I2COV	D_A	P	S	R_W	RBF	TBF	0x0000
Address register

(Table 12-2 continued)

I2CEN – I2C enable bit 
 (I2CEN = 0 I2C module disabled, I2CEN = 1 I2C module enabled and the SDA 
 and SCL pins configured as serial port pins)

I2CSIDL – STOP in IDLE mode bit (I2CSIDL = 0 continue module operation, 
 I2CSIDL = 1 discontinue module operation)

SCREL – SCL pin release control bit (SCREL = 0 hold SCL clock low 
 (clock stretch in slave mode), SCREL = 1 release SCL clock)
 
IPMIEN – Intelligent peripheral management interface enable bit 
 (IPMIEN = 0 IPMI mode not enabled, IPMIEN = 1 enable IPMI support mode)
 
A10M – 10-bit slave address bit 
 (A10M = 0 I2CADD is a 7-bit address, I2CADD = 1 I2CADD is a 10-bit address)
 
DISSLW – Disable slew rate control bit 
 (DISSLW = 0 slew rate control enabled, DISSLW = 1 slew rate control disabled)
 
SMEN – SMBus input levels bit 
 (SMEN = 0 disable SMBus input thresholds, SMEN = 1 enable I/O pin 
 thresholds compliant with SMBus specification)
 
GCEN – General call enable bit (when operating as I2C slave) 
 (GCEN = 0 general call address disabled, GCEN = 1 enable 
 interrupt when a general call address is received in the I2CRSR)
 
STREN – SCL clock stretch enable bit (when operating as I2C slave) 
 (STREN = 0 disable software or receive clock stretching, 
 STREN = 1 enable software or receive clock stretching)
 
ACKDT – Acknowledge data bit (when operating as I2C master, during master receive) 
 (ACKDT = 0 send NACK during Acknowledge, ACKDT = 1 send ACK during Acknowledge)
 
ACKEN – Acknowledge sequence enable bit (when operating as I2C master, during master receive) 
 (ACKEN = 0 acknowledge sequence not in progress, ACKEN = 1 initiate acknowledge 
 sequence on SDA and SCL pins and transmit ACKDT data bit)
 
RCEN – Receive enable bit (when operating as I2C master) 
 (RCEN = 0 receive sequence not in progress, RCEN = 1 enable receive mode for I2C)
 
PEN – STOP condition enable bit (when operating as I2C master) 
 (PEN = 0 STOP condition not in progress, 
 PEN = 1 initiate STOP condition on SDA and SCL pins)
 
RSEN – Repeated START condition enable bit (when operating as I2C master) 
 (RSEN = 0 repeated START condition not in progress, 
 RSEN = 1 initiate repeated START condition on SDA and SCL pins)
 
SEN – START condition enabled bit (when operating as I2C master) 
 (SEN = 0 START condition not in propgress, 
 SEN = 1 initiate START condition on SDA and SCL pins)
 
ACKSTAT – Acknowledge status bit (when operating as I2C master) 
 (ACKSTAT = 0 ACK received from slave, 
 ACKSTAT = 1 NACK received from slave)
 
TRSTAT – Transmit status bit (when operating as I2C master) 
 (TRSTAT = 0 master transmit is not in progress,
 TRSTAT = 1 master transmit is in progress (8 bits + ACK))
 
BCL – Master bus collision detect bit (BCL = 0 no collision, 
 BCL = 1 a bus collision has been detected during a master operation)
 
GCSTAT – General call status bit (GCSTAT = 0 general call address was not received, 
 GCSTAT = 1 general call address was received)
 
ADD10 – 10-bit address status bit 
 (ADD10 = 0 10-bit address was not matched, ADD10 = 1 10-bit address was matched)
 
IWCOL – Write collision detect bit 
 (IWCOL = 0 no collision, IWCOL = 1 an attempt to write the I2CTRN register failed 
 because the I2C module is busy)
 
I2COV – Receive overflow flag bit (I2COV = 0 no overflow, I2COV = 1 a byte was received while
 the I2CRCV register is still holding the previous byte)
 
D_A – Data/address bit (when operating as I2C slave) 
 (D_A = 0 indicates that the last byte received was device address, 
 D_A = 1 indicates that the last byte received was data)
 
P – STOP bit 
 (P = 0 STOP bit was not detected last, 
 P = 1 indicates that a STOP bit has been detected last)
 
S – START bit (S = 0 START bit was not detected last, 
 S = 1 indicates that a START, or repeated START, bit has been detected last)
 
R_W – Read/write bit information (when operating as I2C slave) 
 (R_W = 0 write – indicates data transfer is input to slave, 
 R_W = 1 read - indicates data transfer is output from slave)
 
RBF – Receive buffer full status bit (RBF = 0 receive not complete, 
 I2CRCV is empty, RBF = 1 receive complete, I2CRCV is full)
 
TBF – Transmit buffer full status bit (TBF = 0 transmit complete, 
 I2CTRN is empty, TBF = 1 transmit in progress, I2CTRN is full)