One of the essential improvements which made possible the execution of an instruction in one instruction cycle is hardware multiplier. The input data are 16-bit quantities and the 32-bit output data are extended to 40 bits in order to facilitate adding to the current value in the accumulator. If this multiplier did not exist, multiplying 16-bit quantities would require 16 instruction cycles which would for many digital signal processing applications be unacceptably long.
The values to be multiplied are via the X and Y data buses fed simultaneously to the input of the multiplier. The output of the multiplier is fed to the to the 40 bits extension block retaining the sign.
By multiplying two 16-bit values one obtains a 32-bit value. However, the aim is not only to multiply but also to calculate the sum of the partial products for the whole array. Therefore, multiplying is only one part and the result is a partial sum. The number of the partial sums will correspond to the length of the array. It follows that the 32 bits will not be sufficient for saving the result because the probability of overflow is high. For this reason it is required to extend the value which will be accumulated. It has been adopted that this extention is 8 bits resulting in the total of 40 bits.
In the worst case that all partial sums are the maximum 32-bit value, one can sum 256 partial sums before overflow. This means that the maximum length of an array consisting of 32-bit elements all of the maximum value is 256. For most applications this is sufficient, but such arrays are very rare and the permissible array lengths are several times longer.
Depending on the values of indiviual bits in the CORCON register, the multiplication may be carried out with signed or unsigned integers or signed or unsigned fractionals formated 1.15 (1 bit for sign and 15 bits for value). The most often used format is fractional (radix).