Functional block diagram of the 12-bit A/D converter used in the dsPIC30F4013 microcontroller is shown in Fig. 7-1.

The A/D converter possesses 12 analogue inputs (other microcontrollers of the dsPIC30F family could have up to 16 analogue inputs) connected via an analogue multiplexer to the Sample/Hold amplifier. There are two analogue inputs for setting an external reference voltage. The output of the Sample/Hold amplifier is the input to the converter, based on successive approximations. The 12-bit A/D converter can be configured that the reference voltages are the supply voltages (AVDD, AVSS) or external reference voltages (VREF+, VREF-). This A/D converter can operate in SLEEP mode which is very useful for the purpose of minimizing conversion noise owing to the power supply. For controlling the process of A/D conversion the A/D converter has six 16-bit control registers: registers ADCON1, ADCON2, ADCON3 serving for selecting the mode of the A/D converter, register ADCHS serving for selecting analogue inputs used for A/D conversion, register ADPCFG serving for selecting the pin used as analogue input and the pin used as Input/Output (I/O) pin, and register ADCSSL serving for selecting the analogue inputs to be scanned. The result of A/D conversion is loaded in a «read-only» RAM buffer, 16-word deep and 12-bit wide. The result of conversion from the buffer denoted by ADBUF0, ADBUF1, ... ADBUFF is, via the output 16-bit register, read in accordance with the selected output format. The content of the RAM buffer at locations ADBUF0 to ADBUFF can not be written by software, but is written exclusively by the A/D converter.

7.1.1 A/D conversion sequence

Upon configuration of the A/D converter, the process of acquisition of samples of the input signalis is started by setting the SAMP bit. The conversion may be started by various sources: programmable control bit, timer after a preset time interval, or an external event. When the conversion time is complete, the result is loaded into the RAM buffer located from ADBUF0 to ADBUFF registers. Upon completion of the A/D conversion, the bit DONE and interrupt flag are set after the number of samples defined by the SMPI control bits. The following steps should be followed for performing an A/D conversion:

1. Configure the A/D module
   • configure the port pins as analogue inputs, voltage reference, and digital I/O pins,
   • select A/D converter input channel,
   • select A/D conversion clock,
   • select A/D conversion trigger source,
   • turn on A/D module;
2. Configure A/D interrupt (if required)
   • clear ADIF bit (IFS0,11>),
   • select A/D interrupt priority,
   • set ADIE bit (IEC0<11>);
3. Start sampling
4. Wait the required acquisition time;
5. Trigger acquisition end, start conversion;
6. Trigger acquisition end, start conversion;
7. Wait for A/D to complete, by either
   • waiting for the A/D interrupt, or
   • waiting for the DONE bit to get set;
8. Read A/D result buffer, clear ADIF bit if required.

7.1.2 A/D converter configuration

Select voltage reference – A/D converter configuration is started by selecting the voltage reference source. This process is performed by setting the control bit VCFG<2:0> (ADCON2<15:13>). The reference voltage could be selected to be either internal supply voltages AVDD or AVSS or external voltage references VREF+ or VREF- via the external pins. Select the A/D conversion clock – A/D conversion rate is determined by the A/D conversion clock, the period is denoted by TAD . For performing one A/D conversion 14 periods of the TAD clock are required. The A/D converer clock is formed on the basis of the instruction clock TCY of the microcontroller. The A/D conversion period TAD , generated by a 6-bit counter, is selected by the control bits ADCS<5:0> (ADCON3<5:0>). Period TAD is defined by the formula: In order that the A/D conversion gives a correct result, it is required that the conversion time, 14TAD , is at least 10µs. From this condition one can conclude that the minimum period of the A/D converter clock is TAD = 667ns (applicable to dsPIC30F3014 and dsPIC30F6014A). For the 10-bit A/D converters of the dsPIC30F family the minimum period of the clock is 154ns. Table 7-1 presents the values of the period of the A/D converter clock and the length of A/D conversion as functions of the instruction clock TCY of the micocontroller. Selection of analogue inputs – All Sample/Hold amplifiers have analogue multiplexers for selecting analogue input pins determined by the control bits ADCHS. The control bits ADCHS determine which analogue inputs are selected for each sample (non-inverting and inverting). Configuring analogue port pins – The ADPCFG register specifies the input condition of device pins used as analogue inputs. A pin is configured as an analogue input when the corresponding PCFGn bit (ADPCFG<n>) is cleared. If the corresponding PCFGn is set, the pin is configured as a digital I/O. The ADPCFG register is cleared at RESET, causing the A/D input pins to be configured for analogue inputs. The TRISB register determines whether a digital port is input or output. If the corrsponding TRIS bit is set, the pin is input, if this bit is cleared, the pin is output. Configuration of the ADPCFG and TRISB registers controls the operation of the A/D port pins. Channel 0 input selection – The user may select any of the up to 16 analogue inputs as the input to the positive input of the Sample/Hold amplifier by setting the control bits CH0SA<3:0> (ADCHS<3:0>). The user may select either VREF- or A1 as the negative input of the channel, depending on the setting the CH0NA bit. In this way channel 0 is fully defined. Specifying altenating channel 0 input selections – The ALTS control bit causes the module to alternate between two sets of inputs that are selected during successive samples. The inputs specified by CH0SA<3:0>, CH0NA, CHXSA, and CHXNA<1:0> are collectively called the MUX A inputs. The inputs specified by CH0SB<3:0>, CH0NB, CHXSB, and CHXNB<1:0> are collectively called the MUX B inputs. When the ALTS control bit is set, then one input of the group MUX A and one input of the group MUX B are selected alternatively. When this control bit is cleared, only the group MUX A inputs are selected for sampling. Scanning through several inputs with channel 0 – Channel 0 has the ability to scan through a selected vector of inputs. The CSCNA bit (ADCON2<10>) enables the CH0 channel inputs to be scanned across a selected number of analogue inputs. When CSCNA bit is set, the CH0SA<3:0> bits are ignored. The ADCSSL register specifies the inputs to be scanned. Each bit in the ADCSSL register corresponds to an anlogue input (bit 0 corresponds to AN0, bit 1 to AN1, etc.). If the bit of the corresponding input is set, the selected input is the part of the scanning sequence. The inputs are always scanned from the lower to the higher numbered inputs. The control register ADCSSL only specifies the input of the positive input of the channel. The CH0NA bit still selects the input of the negative input of the channel during scanning. If the alternate selection ALTS control bit is set, the scanning only applies to the MUX A (CH0SA<3:0>) input selection. The same applies for the MUX B input selection (CH0SB<3:0>) if selected by the ADCSSL control register. Enabling the A/D converter module – When the ADON bit (ADCON1<15>) is set, the module is in active mode and is fully powered and functional. When the ADON bit is cleared, the module is disabled. The digital and analogue portions of the circuit are turned off for maximum current savings.

7.1.3 Starting A/D conversion process – start of the sampling process

Depending on the A/D converter mode selected, the sampling and conversion processes can be started manually or automatically. By starting the conversion process the sampling process on the Sample/Hold amplifier is started. Manual start of the sampling process – Setting the SAMP bit (ADCON1<1>) causes the A/D converter to begin sampling. One of several options can be used to end sampling and complete the conversiton.Sampling will not resume until the SAMP bit is once again set. Fig. 7-2 shows an example of the manual sample start. Automatic start of the sampling process – Setting the ASAM bit (ADCON1<2>) causes the A/D converter to automaticaaly begin sampling whenever previous conversion cycle is completed. One of several options can be used to end sampling and complete the conversion. Sampling resumes after the conversion is completed. Fig. 7-3 shows an example of the automatic sample start.

7.1.4 Stopping sampling and starting conversions

The conversion trigger source will terminate sampling and start the sequence of conversions. The SSRC<2:0> control bits (ADCON1<7:5>) select the source of the conversion trigger. Similarly to starting sampling process, a user can start conversions manually or automatically. Manual conversion start – When SSRC<2:0>=000, the conversion trigger is under software control. Clearing the SAMP bit (ADCON1<1>) strts the conversion sequence. Fig. 7-2 is an example of the manual start of the conversion sequence. The figure shows manual sample start by setting the SAMP bit (SAMP=1) and manual conversion start by clearing the SAMP bit (SAMP=0). The user must time the setting and clearing the SAMP bit in accordance with the acquisition time TSAMP of the input signal.

Example:

This example shows a manual sample start and a manual conversion start. The result of the A/D conversion is sent to the output of port D.

/* device = dsPIC30F6014A
 Clock=10MHz */

void main(){
 TRISB = 0xFFFF; //Port B is input
 TRISD = 0; //Port D is output (for ADC results)
 ADPCFG = 0xFBFF; //10th channel is sampled and coverted
 ADCON1 = 0; //ADC off, output_format=INTEGER
 //Manual start of convesion
 //Manual start of sampling
 ADCHS = 0x000A; //Connect RB10 on AN10 as CH0 input
 ADCSSL = 0; //No scan
 ADCON3 = 0x1003; //ADCS=3 (min TAD for 10MHz is 3*TCY=300ns)
 ADCON2 = 0; //Interrupt upon completion of one sample/convert
 ADCON1.F15 = 1; //ADC on
 while (1) {
 ADCON1.F1 = 1; //Start sampling (SAMP=1)
 Delay_ms(100); //Wait for 100ms (sampling ...)
 ADCON1.F1 = 0; //Clear SAMP bit (trigger conversion)
 while (ADCON1.F0 == 0)
 asm nop; //Wait for DONE bit in ADCON1
 LATD = ADCBUF0; //Output result on port D
 }
}

Fig. 7-3 shows an example of an automatic sample start by setting the control bit ASAM (ASAM=1) and a manual conversion start by clearing the control bit SAMP (SAMP=0). Fig. 7-3 shows that by setting the control bit ASAM the automatic sample start is configured; by clearing the control bit SAMP the sampling process is completed and the process of conversion started. Upon completion of the conversion process, A/D converter automatically starts new sampling process by automatically setting the control bit SAMP. When clearing the control bit SAMP the user software has to take into account the minimum acquisition time and the length of the conversion process.

Example:

This example shows an automatic sample start and a manual conversion start. The result of the conversion is sent to the output of port D.

/*device = dsPIC30F6014A
 Clock=10MHz*/
 
void main(){
 TRISB = 0xFFFF; //Port B is input
 TRISD = 0; //Port D is output (for ADC results)
 ADPCFG = 0xFBFF; //10th channel is sampled and coverted
 ADCON1 = 0x0004; //ADC off, output_format=INTEGER
 //Manual start of convesion
 //Automatic start of sampling after coversion
 ADCHS = 0x000A; //Connect RB10 on AN10 as CH0 input
 ADCSSL = 0; //No scan
 ADCON3 = 0x1003; //ADCS=3 (min TAD for 10MHz is 3*TCY=300ns)
 ADCON2 = 0; //Interrupt upon completion of one sample/convert
 ADCON1.F15 = 1; //ADC on
 while(1){ 
 Delay_ms(100); //Wait for 100ms (sampling ...)
 ADCON1.F1 = 0; //Clear SAMP bit (trigger conversion)
 while(ADCON1.F1 == 0)
 asm nop; //Wait for DONE bit in ADCON1
 LATD = ADCBUF0; //Output result on port D
 }
}

7.1.5 External event trigger conversion start

It is often desirable to synchronize the end of sampling and the start of conversion with some external event, i.e. with an external signal source. The A/D module may use one of three sources as a conversion trigger. External INT pin trigger – When SSRC<2:0>= 001, the A/D conversion is triggered by an active transition on the INT0 pin. The INT0 pin may be programmed for either a rising edge input or a falling edge input. GP timer compare trigger – This mode is also called trigger mode. By setting the control bits SSRC<2:0>=010, the conversion trigger source can be the general purpose 32-bit timer module 2/3. When the value of the TMR3/TMR2 counter register is equal to the value of the preset (period) register PR3/PR2, a special ADC event signal is generated which triggers the conversion process. Motor control PWM trigger – In the microcontrollers containing this module, like the family dsPIC30F60xx, the start of conversion can be synchronized to the PWM time base. When SSRC<2:0>=011, the A/D sampling and conversion time occur at any user programmable point within the PWM period. In this way the user can minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. The descibed modes of external initiation or stopping the sampling process or starting the conversion process by setting the control bits SSRC<2:0> = 001, or 010, or 011 could be combined with the automatic sample start by setting the ASAM bit. Figs. 7-6 and 7-7 give examples of initiating the convesrion process with the manual and automatic sample start, respectively.

Example:

This example shows automatic sample start and start of conversion by timer 3. The result of the conversion is sent to the output of port D.

/*device = dsPIC30F6014A
 Clock=10MHz*/

void main(){
 TRISB = 0xFFFF; //Port B is input
 TRISD = 0; //Port D is output (for ADC results)
 ADPCFG = 0xFBFF; //10th channel is sampled and coverted
 ADCON1 = 0x0040; //ADC off, output_format=INTEGER
 //Timer 3 starts convesion
 ADCHS = 0x000A; //Connect RB10 on AN10 as CH0 input
 ADCSSL = 0; //No scan
 ADCON3 = 0x0F00; //TAD = internalTCY
 //Sample time ends with timer 3 clock
 /*TIMER3 init*/
 TMR3 = 0; //Reset TIMER3 counter
 PR3 = 0x3FFF; //PR3, number of TIMER3 clocks between two conversions start
 T3CON = 0x8010; //TIMER3 ON, prescale 1:1

 ADCON1.F15 = 1; //ADC on
 ADCON1.F2 = 1; //ASAM=1, start sampling after conversion ends
 while(1){
 ADCON1.F1 = 1; //SAMP=1, start sampling
 while(ADCON1.F0 == 0)
 asm nop; //Wait for DONE bit in ADCON1
 LATD = ADCBUF0; //Output result on port D
 }
}

7.1.6 Controlling sample/conversion operation

The application software may poll the SAMP and CONV bits to keep track of the A/D conversions. Alternatively, the module can generate an interrupt (ADIF) when conversions are complete. The application software may also abort A/D operations if necessary. Monitoring sample/conversion status – The SAMP (ADCON1<1>) and CONV (ADCON1<0>) bits idicate the sampling state and the conversion state of the A/D, respectively. Generally, when the SAMP bit clears indicating end of sampling, the CONV bit is automatically set indicating start of conversion. Clearing of the CONV bit denotes end of conversion.. If both SAMP and CONV bits are 0, the A/D is in an inactive state. In some operational modes, the SAMP bit may also invoke and terminate sampling and the CONV bit may terminate conversion. Generating an A/D interrupt - The SMPI<3:0> bits control the generation of interrupts. The interrupt will occur after the number of sample/conversion sequences specified by the SMPI bits and re-occur on each equivalent number of samples. The vaule specified by the SMPI bits will correspond to the number of data samples in the RAM buffer, up to the maximum of 16. Disabling the A/D interrupt is not done with the SMPI bits. To disable the interrupt, clear the ADIE (IEC0<11>) analogue module interrupt enable bit. Aborting sampling – Clearing the SAMP bit while in manual sampling mode will terminate sampling, but may also start a conversion if SSRC= 000. Clearing the ASAM bit while in automatic sampling mode will not terminatean on going sample/convert sequence, however, sampling will not automatically resume after a subsequent conversion. Aborting a conversion – Clearing the ADON bit during a conversion will abort the current conversion. The A/D result will not be updated with the partially completed A/D conversion, i.e. the corresponding ADCBUFi buffer will contain the value od the last completed conversion (or the last value written to the buffer).

7.1.7 Writing conversion results into the buffer

As conversions are completed, the module writes the results of the conversions into the RAM buffer. This buffer is a RAM array of sixteen 12-bit words. The buffer is accessed through the 16 address locations within the SFR space, named ADBUF0, ADBUF1... ADBUFF. User software may attempt to read each A/D result as it is generated, but this might consume too much CPU time. Generally, the module will fill the buffer with several A/D conversion results and then generate an interrupt. This allows accomplishment of high sampling rates. Number of conversions per interrupt – The SMPI<3:0> bits (ADCON2<5:2>) will select how many A/D conversions will take place before the CPU is interrupted. This number can vary from 1 to 16 samples per interrupt. The conversion results will always be written to ADCBUF0, ADCBUF1... ADCBUFF. If SMPI<3:0>= 0000, an interrupt is generated after each conversion and the result is always written in ADCBUF0. Buffer fill mode – In this mode two 8-word groups of the RAM buffer memory will alternately receive the conversion results after each interrupt. This mode is selected by setting the control bit BUFM (ADCON2<1>). While one group receives the A/D conversion results, the content of the other group may be moved to the data memory. In this way the CPU time i saved and high sampling rates can be accomplished. Upon initialization of this mode, by setting the value of the SMPI bit to n (n = 8), the result of each A/D conversion will be loaded to the lower group of the RAM buffer memory, i.e. to the locations ADBUF0 to ADBUF7. After n A/D conversions are completed, an A/D converter interrupt generated, and the interrupt routine carried out, the higher group of the RAM buffer memory, ADBUF8 to ADBUFF, is selected and the results of the next n A/D conversions (n = 8) are loaded to these locations. This mode is selected when the processor cannot unload the RAM buffer within one sample and conversion time sequence.

7.1.8 A/D sampling requirements

For proper functioning of the A/D converor the total sampling time should take into acount the sample/hold amplifier settling time, holding capacitor charge time, and temperature. The analogue input model of the A/D converter is shown in Fig.7-8. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analogue input pin (VA). The source impedance (RS) and the internal sampling switch impedance (RSS) directly affect the time required to charge the capacitor CHOLD. Furthermore, the sampling switch impedance (RSS) varies with the device supply voltage VDD. All these influences, however small, affect the total sampling time of the A/D converter. To avoid exceeding the limit of the sampling time and to minimize the effects of pin leakage currents on the accuracy of the A/D converter, the maximum recommended source impedance (RS) is 2.5kO. To calculate the sampling capacitor charging time the following equation may be used: TSAMP = TAMP + TC +TCOEF , where TSAMP is the total sampling time, TAMP is the sample/hold amplifier settling time, TC is the holding capacitor charging time, and TCOEF is the time due to temperature variation. A/D holding capacitor charging time is given by: TC = -CHOLD(RIC + RSS + RS)ln(1/2n) in seconds, where n is the number of levels of the A/D converter (for a 12-bit A/D converter this is 4096). The time due to temperture dependence of the A/D converter is given by: TCOEF = (Temp – 25C)(0.005µs/C).

Example:

For the values: CHOLD=18pF, RIC = 250O, minimum RS =1O, n=4096 for the full range of a 12-bit A/D converter, VDD=5V, RSS =1.2kO, and operating temperature 25C the following times are obtained TC =0.24µs and TSAMP =0.74 µs. For the values: CHOLD=18pF, RIC = 250O, maximum RS =2.5kO, n=4096 for the full range of a 12-bit A/D converter, VDD=5V, RSS =1.2kO, and operating temperature 25C the following times are obtained TC =0.641 µs and TSAMP =1.14 µs.

7.1.9 Reading the A/D result buffer

The results of A/D conversions are loaded into the 16-word 12-bits wide RAM buffer. Reading the RAM buffer is possible from the special function register memory locations ADBUF0 to ADBUFF in one of the four selectable formats: integer, signed integer, fractional, and signed fractional. The FORM<1:0> bits (ADCON1<9:8>) select the format. Fig. 7-9 shows the data output formats of the A/D converter.

7.1.10 Operation during SLEEP and IDLE modes

During SLEEP or IDLE modes, depending upon the configuration, the operation of the A/D converter is possible. These modes are useful for minimizing conversion noise because the digital activity of the CPU, buses, and other peripherals is minimized. Operation in SLEEP mode without RC A/D clock – If the internal RC clock generator is not used, when the device enters SLEEP mode, all clock sources to the module are shut down. If SLEEP occurs in the middle of a conversion, the conversion is aborted. The converter will not resume a partially completed conversion on exiting from SLEEP mode. Register contents are not affected by the device entering or leaving SLEEP mode. Operation in SLEEP mode with RC A/D clock – If the A/D clock source is set to the internal RC oscillator (ADRC=1), the A/D module can operate during SLEEP mode. This eliminates digital switching noise. When the conversion is completed, the CONV bit will be cleared and the result loaded into the RAM buffer. If the interrupt is enabled ADIE=1 (IEC0<11>), the device will wake-up from SLEEP when the A/D interrupt occurs ADIF=1 (IPS0<11>). The interrupt service routine will be carried out if the A/D’interrupt is greater than the current CPU priority. Otherwise, the device returns to SLEEP mode. If the A/D interrupt is not enabled, the A/D module will then be turned off while the ADON bit remains set. To minimize the effects of digital noise on the A/D module operation, the user shoud select a convesrion trigger source before the microcontroller enters SLEEP mode. The control bits SSRC<2:0>=111 are set befor the PWRSAV instruction. Operation during IDLE mode – If the control bit ADIDL (ADCON1<13>) is cleared, the A/D module will continue normal operation in IDLE mode. If the A/D interrupt is enabled (ADIE=1), the device will wake-up from IDLE mode when the A/D interrupt occurs. The A/D interrupt service routine will be carried out if the A/D interrupt is greater than the current CPU priority. Otherwise, the device returns to IDLE mode. If A/D interrupt is disabled, the A/D module will be turned off while the ADON bit remains set. If the control bit ADIDL is set, the module will stop in IDLE mode. If the device enters IDLE mode in the middle of a conversion, the conversion is aborted. The converter will not resume a partially completed conversion on exiting from IDLE mode. Finally, the desriptions of the A/D module control registers are presented.

NAME	ADR	15-12	11	10	9	8	7	6	5	4	3	2	1	0	RESET STATE
ADBUF0	0x0208	-	ADC DATA BUFFER 0												0x0uuu
ADBUF1	0x0208	-	ADC DATA BUFFER 1												0x0uuu
ADBUF2	0x0208	-	ADC DATA BUFFER 2												0x0uuu
ADBUF3	0x0208	-	ADC DATA BUFFER 3												0x0uuu
ADBUF4	0x0208	-	ADC DATA BUFFER 4												0x0uuu
ADBUF5	0x0208	-	ADC DATA BUFFER 5												0x0uuu
ADBUF6	0x0208	-	ADC DATA BUFFER 6												0x0uuu
ADBUF7	0x0208	-	ADC DATA BUFFER 7												0x0uuu
ADBUF8	0x0208	-	ADC DATA BUFFER 8												0x0uuu
ADBUF9	0x0208	-	ADC DATA BUFFER 9												0x0uuu
ADBUFA	0x0208	-	ADC DATA BUFFER 10												0x0uuu
ADBUFB	0x0208	-	ADC DATA BUFFER 11												0x0uuu
ADBUFC	0x0208	-	ADC DATA BUFFER 12												0x0uuu
ADBUFD	0x0208	-	ADC DATA BUFFER 13												0x0uuu
ADBUFE	0x0208	-	ADC DATA BUFFER 14												0x0uuu
ADBUFF	0x0208	-	ADC DATA BUFFER 15												0x0uuu

Table 7-2 Description of the RAM buffer registers.

NAME	ADR	15	14	13	12-10	9	8	7-5	4-3	2	1	0	RESET STATE
ADCON1	0x02A0	ADON	-	ADIDL	-	FORM<1:0>		SSRC<2:0>		ASAM	SAMP	CONV	0x0000

Table 7-3 Description of the configuration register ADCON1

ADON – A/D operating mode bit 
 (ADON=1 A/D converter module is operating, ADON=0 A/D converter is off)
ADIDL – Stop in IDLE mode bit (ADIDL=1 discontinue module operation when device enters 
 IDLE mode, ADIDL=0 continue module operation in IDLE mode)
FORM<1:0> - Data output format bits
 00 – integer
 01 – signed integer
 10 – fractional
 11 – signed fractional
SSRC<2:0> - Conversion trigger source select bit
 000 – clearing SAMP bit ends sampling and starts conversion
 001 – active transition on INTO pin ends sampling and starts conversion
 010 – general purpose timer3 compare ends sampling and starts conversion
 011 – motor control PWM interval ends sampling and starts conversion
 101...110 – reserved 
 111 – automatic mode
ASAM – A/D sample auto-START bit
SAMP – A/D sample enable bit (SAMP=1 at least one A/D sample/hold amplifier sampling,
 SAMP=0 sample/hold amplifiers are holding)
DONE – A/D conversion status bit 
 (DONE=1 A/D conversion is done, DONE=0 A/D conversion is in progress)

NOTE: Unimplemented bits read "0".

NAME	ADR	15-13	12-11	10	9-8	7	6	5	4	3	2	1	0	RESET STATE
ADCON2	0x02A2	VCFG<2:0>	-	CSCNA	-	BUFS	-	SMPI<3:0>				BUFM	ALTS	0x0000

Table 7-4 Description of the configuration register ADCON2

VCFG<2:0> - Voltage reference configuration bit
 000 - VREFH =AVDD, VREFL=AVSS
 001 - VREFH= External VREF+ pin, VREFL=AVSS
 010 - VREFH =AVDD, VREFL=External VREF- pin
 011 - VREFH= External VREF+ pin, VREFL=External VREF- pin
 1xx - VREFH =AVDD, VREFL=AVSS
CSCNA - Scan input selections for CH0+ S/H input for MUX A input multiplexer setting bit
BUFS - Buffer full status bit
 Only valid when BUFM=1 (ADRES split into 2 x 8-word buffers)
 BUFS=1 A/D is currently filling higher buffer 0x8-0xF, 
 BUFS=0 A/D is currently filling lower buffer 0x0-0x7
SMPI<3:0> - Sample/convert sequences per interrupt selection bits
 0000 - interrupts at the completion of conversion for each sample/convert sequence
 0001 - interrupts at the completion of conversion for each 2nd sample/convert sequence
 ...
 1110 - interrupts at the completion of conversion for each 15th sample/convert sequence
 1111 - interrupts at the completion of conversion for each 16th sample/convert sequence
BUFM - Buffer mode select bit (BUFM=1 Buffer configured as two 8-word buffers 
 ADCBUF(15...8), ADCBUF(7...0), 
 BUFM=0 Buffer configured as one 16-word buffer ADCBUF(15...0))
ALTS - Alternate input sample mode select bit 
 (ALTS=1 alternate sampling enabled, ALTS=0 always use MUX A input)

NOTE: Unimplemented bits read "0".

NAME	ADR	15-13	12	11	10	9	8	7	6	5	4	3	2	1	0	RESET STATE
ADCON3	0x02A4	-	SAMC<4:0>					ADRC	-	ADCS<5:0>						0x0000

Table 7-5 Description of the configuration register ADCON3

SAMC<4:0> - Auto sample time bits
 00000 - 0 TAD
 00001 - 1 TAD
 ...
 11111 - 31 TAD
ADRC - A/D conversion clock source bit (ADRC=1 A/D internal RC clock, 
 ADRC=0 Clock derived from system clock)
ADCS<5:0> - A/D conversion clock select bits
 000000 - TCY/2 * (ADCS<5:0> + 1)=TCY/2
 000001 - TCY/2 * (ADCS<5:0> + 1)=TCY
 ...
 111111 - TCY/2 * (ADCS<5:0> + 1)=32*TCY

NOTE: Unimplemented bits read "0".

NAME	ADR	15-13	12	11	10	9	8	7	6	5	4	3	2	1	0	RESET STATE
ADCHS	0x02A6	-	CH0NB	CH0SB<3:0>				-	-	-	CH0NA	CH0SA				0x0000

Table 7-6 Description of the ADCHS configuration register

CH0NB - Channel 0 negative input select for MUX B multiplexer setting bit 
 (CH0NB=1 input AN1 selected, CH0NB=0 input VREF- selected)
CH0SB<3:0> - Channel 0 positive input select for MUX B multiplexer setting bit
 0000 - input AN0 selected 
 0001 - input AN1 selected
 ...
 1110 - input AN14 selected
 1111 - input AN15 selected
CH0NA - Channel 0 negative input select for MUX A multiplexer setting bit 
 (CH0NA=1 input AN1 selected, CH0NA=0 input VREF- selected)
CH0SA<3:0> - Channel 0 positive input select for MUX A multiplexer setting bit
 0000 - input AN0 selected 
 0001 - input AN1 selected
 ...
 1110 - input AN14 selected
 1111 - input AN15 selected

NAME	ADR	15-0	RESET STATE
ADPCFG	0x02A8	PCFG<15:0>	0x0000

Table 7-7 Description of the ADPCFG configuration register

PCFG<15:0> - Analogue input pin configuration control bits
(PCFG(i)=1 pin ANi configured as digital I/O pin, 
PCFG(i)=0 pin ANi configured as analogue input pin)

NAME	ADR	15-0	RESET STATE
ADCSSL	0x02AA	ADC Input scan select register	0x0000

Table 7-8 Description of the ADCSSL configuration register

ADCSSL<15:0> - A/D input pin scan selection bits