Timer2 is an 8-bit timer which operates in a specific way.

Pulses generated by the quartz oscillator first pass through the prescaler the rate of which may be changed using the T2CKPS1 and T2CKPS0 bits. The output of the prescaler is then used to increment the TMR2 register starting at 00h. The values of TMR2 and PR2 registers are compared all the time and the TMR2 is constantly incremented until it matches the value stored in PR2. When the match occurs, the TMR2 register is automatically cleared. The Timer2 postscaler is incremented on every match and its output is used to generate an interrupt if enabled. The TMR2 and PR2 registers are both readable and writable. Counting may be stopped by clearing the TMR2ON bit, thus reducing power consumption. The moment of the Timer2 reset may also be used as a serial communication clock signal. The operation of the Timer2 is under control of several bits of the T2CON register.

T2CON Register

TOUTPS3 - TOUTPS0 - Timer2 Output Postcaler Select bits are used to determine the postscaler rate according to the following table:

TOUTPS3	TOUTPS2	TOUTPS1	TOUTPS0	POSTSCALER RATE
0	0	0	0	1:1
0	0	0	1	1:2
0	0	1	0	1:3
0	0	1	1	1:4
0	1	0	0	1:5
0	1	0	1	1:6
0	1	1	0	1:7
0	1	1	1	1:8
1	0	0	0	1:9
1	0	0	1	1:10
1	0	1	0	1:11
1	0	1	1	1:12
1	1	0	0	1:13
1	1	0	1	1:14
1	1	1	0	1:15
1	1	1	1	1:16

TMR2ON - Timer2 On bit turns the Timer2 on.

• 1 - Timer2 is on.
• 0 - Timer2 is off.

T2CKPS1, T2CKPS0 - Timer2 Clock Prescale bits determine the prescaler rate:

T2CKPS1	T2CKPS0	PRESCALER RATE
0	0	1:1
0	1	1:4
1	x	1:16