The watchdog timer uses pulses generated by the quartz oscillator for its operation. It is disabled after reset and during Power Down Mode, thus having no effect on the program execution. If enabled, every time it counts up to the program end, the microcontroller reset occurs and program execution starts from the first instruction. Reset condition indicates that the program doesn’t work properly for some reason. The point is to prevent this from happening by setting instruction to reset the watchdog timer at the appropriate program location. Practically, the whole this process is in control of several bits of the WDTCON register.

Three bits (PS2, PS1 and PS0), which are in control of the prescaler, determine the most important feature of the watchdog timer- nominal time, i.e. time required to count up a full cycle. The values contained in the table below are applied only when the 12MHz quartz oscillator is used.

PRESCALER BITS			NOMINAL TIME
PS2	PS1	PS0
0	0	0	16ms
0	0	1	32ms
0	1	0	64ms
0	1	1	128ms
1	0	0	256ms
1	0	1	512ms
1	1	0	1024ms
1	1	1	2048ms

WDTCON Register (Watchdog Control Register)

PS2,PS1,PS0 These three bits are in control of the prescaler and determine the nominal time of the watchdog timer. If the program doesn’t clear the WSWRST bit during that time, the watchdog timer will reset the microcontroller. When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K machine cycles. When all three bits are set to 1, the nominal period is 2048K machine cycles. WDIDLE The WDIDLE bit enables/disables the watchdog timer in Idle mode:

• 0 - Watchdog timer is enabled in Idle mode (low-consumption mode).
• 1 - Watchdog timer is disabled in Idle mode.

DISRTO The DISRTO bit enables/disables reset of peripheral circuits connected to the RST pin:

• 0 - Watchdog controls the state of the input reset pin. At the moment of reset, this pin acts for a moment as an output and generates a logic one (1). It causes the microcontroller and all other circuits connected to the RST pin to be reset.
• 1 - Reset triggered by the watchdog timer doesn’t affect the state of the reset pin. At the moment the watchdog timer resets the microcontroller, the reset pin remains configured as an input.

HWDT The HWDT bit selects hardware or software mode for the watchdog timer:

• 0 - Watchdog is in software mode and can be enabled or disabled by the WDTEN bit.
• 1 - Watchdog is in hardware mode. To enable it, the sequence 1E/E1(hex) should be written to the WDTRST register. Only reset condition can disable the watchdog timer. In order to prevent the WCDT from resetting the microcontroller when the nominal time expires, the same sequence 1E/E1hex must be constantly repeated.

WSWRST When set, this bit resets the watchdog timer in software mode (bit HWDT=0). In order to enable the microcontroller to operate without being interrupted, this bit must regularly be cleared from within the program. After being set, the watchdog timer is cleared by hardware, counting starts from zero and the bit is automatically cleared. If the watchdog timer is in hardware mode, setting this bit has no effect on the watchdog timer operation. WDTEN The WDTEN bit enables/disables the watchdog timer in software mode (HWDT=0):

• 0 - Watchdog disabled.
• 1 - Watchdog enabled.

When the watchdog timer is in hardware mode (HWDT=1), this bit is read-only and reflects the status of the watchdog timer (whether it is enabled or disabled).