Hello,
My project is PIC18F4620 and ENC28J60. I used Mikroe's example of httpserver that works perfectly (just changed few things to switch from 16F877 in the example to 18F4620 in my project).
Question : I would like to use the power saving feature in the ENC28J60, and control this feature with the PIC : how to access ENC28J60's registers, especially ECON2:PWRSV ? With SPI_ethernet microbasic commands that are available or do I need other routines ?
ENC28J60 registers
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tihomir.losic
- mikroElektronika team
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Hello,
Here are the texts from the Datasheet for the ENC28J60 describing the power saving feature.
POWER SAVER
The ENC28J60 may be commanded to power-down via the SPI interface. When powered down, it will no longer be able to transmit and receive any packets.
To maximize power savings:
1. Turn off packet reception by clearing ECON1.RXEN.
2. Wait for any in-progress packets to finish being received by polling ESTAT.RXBUSY. This bit should be clear before proceeding.
3. Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
4. Set ECON2.VRPS (if not already set).
5. Enter Sleep by setting ECON2.PWRSV. All MAC, MII and PHY registers become inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
In Sleep mode, all registers and buffer memory will maintain their states. The ETH registers and buffer memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see Section “CLKOUT Pin”).
When normal operation is desired, the host controller must perform a slightly modified procedure:
1. Wake-up by clearing ECON2.PWRSV.
2. Wait at least 300 μs for the PHY to stabilize. To accomplish the delay, the host controller may poll ESTAT.CLKRDY and wait for it to become set.
3. Restore receive capability by setting
ECON1.RXEN.
After leaving Sleep mode, there is a delay of many milliseconds before a new link is established (assuming an appropriate link partner is present). The host controller may wish to wait until the link is established
before attempting to transmit any packets. The link status can be determined by polling the PHSTAT2.LSTAT bit. Alternatively, the link change interrupt may be used if it is enabled. See Section “Link Change Interrupt Flag (LINKIF)” for additional details.
CLKOUT Pin
The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register.
To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting.
When the OST expires, the CLKOUT pin will begin outputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT function
will not be altered (ECOCON will not change value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the
OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low.
Link Change Interrupt Flag (LINKIF)
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the PHSTAT1.LLSTAT or PHSTAT2.LSTAT. Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To receive it, the host controller must set the PHIE.PLNKIE and PGEIE bits. After setting the two PHY interrupt enable bits, the LINKIF bit will then shadow the contents of the PHIR.PGIF bit. The PHY only supports one interrupt, so the PGIF bit will always be the same as the PHIR.PLNKIF bit (when both PHY
enable bits are set).
Once LINKIF is set, it can only be cleared by the host controller or by a Reset. If the link change interrupt is enabled (EIE.LINKIE = 1, EIE.INTIE = 1, PHIE.PLNKIE = 1 and PHIE.PGEIE = 1), an interrupt will be generated by driving the INT pin low. If the link change interrupt is not enabled (EIE.LINKIE = 0, EIE.INTIE = 0, PHIE.PLNKIE = 0 or PHIE.PGEIE = 0), the host controller may poll the ENC28J60 for the PHIR.PLNKIF bit and take appropriate action. The LINKIF bit is read-only. Because reading from PHY registers requires non-negligible time, the host controller may instead set PHIE.PLNKIE and PHIE.PGEIE and then poll the EIR.LINKIF bit. Performing an MII read on the PHIR register will clear the LINKIF, PGIF and PLNKIF bits automatically and allow for future link status
change interrupts.
I hope it will help to you.
Best regards,
Losic Tihomir
Here are the texts from the Datasheet for the ENC28J60 describing the power saving feature.
POWER SAVER
The ENC28J60 may be commanded to power-down via the SPI interface. When powered down, it will no longer be able to transmit and receive any packets.
To maximize power savings:
1. Turn off packet reception by clearing ECON1.RXEN.
2. Wait for any in-progress packets to finish being received by polling ESTAT.RXBUSY. This bit should be clear before proceeding.
3. Wait for any current transmissions to end by
confirming ECON1.TXRTS is clear.
4. Set ECON2.VRPS (if not already set).
5. Enter Sleep by setting ECON2.PWRSV. All MAC, MII and PHY registers become inaccessible as a result. Setting PWRSV also
clears ESTAT.CLKRDY automatically.
In Sleep mode, all registers and buffer memory will maintain their states. The ETH registers and buffer memory will still be accessible by the host controller.
Additionally, the clock driver will continue to operate.
The CLKOUT function will be unaffected (see Section “CLKOUT Pin”).
When normal operation is desired, the host controller must perform a slightly modified procedure:
1. Wake-up by clearing ECON2.PWRSV.
2. Wait at least 300 μs for the PHY to stabilize. To accomplish the delay, the host controller may poll ESTAT.CLKRDY and wait for it to become set.
3. Restore receive capability by setting
ECON1.RXEN.
After leaving Sleep mode, there is a delay of many milliseconds before a new link is established (assuming an appropriate link partner is present). The host controller may wish to wait until the link is established
before attempting to transmit any packets. The link status can be determined by polling the PHSTAT2.LSTAT bit. Alternatively, the link change interrupt may be used if it is enabled. See Section “Link Change Interrupt Flag (LINKIF)” for additional details.
CLKOUT Pin
The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register.
To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting.
When the OST expires, the CLKOUT pin will begin outputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT function
will not be altered (ECOCON will not change value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the
OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low.
Link Change Interrupt Flag (LINKIF)
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the PHSTAT1.LLSTAT or PHSTAT2.LSTAT. Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To receive it, the host controller must set the PHIE.PLNKIE and PGEIE bits. After setting the two PHY interrupt enable bits, the LINKIF bit will then shadow the contents of the PHIR.PGIF bit. The PHY only supports one interrupt, so the PGIF bit will always be the same as the PHIR.PLNKIF bit (when both PHY
enable bits are set).
Once LINKIF is set, it can only be cleared by the host controller or by a Reset. If the link change interrupt is enabled (EIE.LINKIE = 1, EIE.INTIE = 1, PHIE.PLNKIE = 1 and PHIE.PGEIE = 1), an interrupt will be generated by driving the INT pin low. If the link change interrupt is not enabled (EIE.LINKIE = 0, EIE.INTIE = 0, PHIE.PLNKIE = 0 or PHIE.PGEIE = 0), the host controller may poll the ENC28J60 for the PHIR.PLNKIF bit and take appropriate action. The LINKIF bit is read-only. Because reading from PHY registers requires non-negligible time, the host controller may instead set PHIE.PLNKIE and PHIE.PGEIE and then poll the EIR.LINKIF bit. Performing an MII read on the PHIR register will clear the LINKIF, PGIF and PLNKIF bits automatically and allow for future link status
change interrupts.
I hope it will help to you.
Best regards,
Losic Tihomir
mikroElektronika [Support team]
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tihomir.losic
- mikroElektronika team
- Posts: 2138
- Joined: 02 Dec 2009 14:16
- Location: Serbia
- Contact:
Hello,
1. If you are using our SPI Ethernet Library, you should analyze the examples provided for it, got the the idea what general concepts are used for this.
2. If you want to implement some of your own routines, please study thoroughly ENC28J60 datasheet (http://ww1.microchip.com/downloads/en/D ... 39662a.pdf), and search in mikroC's Uses folder for low-level routines that you can use in the implementation of your own functions. You have information on this in the Help file.
3. We are sorry, but it is our management's decision that source codes are not available for viewing.
Best regards,
Losic Tihomir
1. If you are using our SPI Ethernet Library, you should analyze the examples provided for it, got the the idea what general concepts are used for this.
2. If you want to implement some of your own routines, please study thoroughly ENC28J60 datasheet (http://ww1.microchip.com/downloads/en/D ... 39662a.pdf), and search in mikroC's Uses folder for low-level routines that you can use in the implementation of your own functions. You have information on this in the Help file.
3. We are sorry, but it is our management's decision that source codes are not available for viewing.
Best regards,
Losic Tihomir
mikroElektronika [Support team]
I thank you for the answer and I understood that I will have some stuff to achieve my goal.
Too bad that a procedure like SPI_ethernet_read_register (or write) doesn't exist in Mikrobasic, it should have been possible to use all the ENC28J60 possibilities.
On the other hand, having to create these routines myself will improve my knowledge.
Best regards
Too bad that a procedure like SPI_ethernet_read_register (or write) doesn't exist in Mikrobasic, it should have been possible to use all the ENC28J60 possibilities.
On the other hand, having to create these routines myself will improve my knowledge.
Best regards
Hello,
I found this :http://www.mikroe.com/upld/enc28j60_libprivate.ppas
which gave me all what I needed. I save a great time and posted the link here for those who are interested.
Best regards
I found this :http://www.mikroe.com/upld/enc28j60_libprivate.ppas
which gave me all what I needed. I save a great time and posted the link here for those who are interested.
Best regards
-
blackbunny
- Posts: 1
- Joined: 02 May 2012 12:11
Re: ENC28J60 registers
HI, apologyse for this offtime question.
How is clocked the 16F877?... in help this pin is not clear...
i think to clkout of enc28j60 or to another clock source?... for what reason in the example are not show the XTAL osc?
thank you, and sorry again for my english and offdate post.
How is clocked the 16F877?... in help this pin is not clear...
i think to clkout of enc28j60 or to another clock source?... for what reason in the example are not show the XTAL osc?
thank you, and sorry again for my english and offdate post.
