Why must the extended instruction set be disabled?

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pizon
mikroElektronika team
Posts: 823
Joined: 11 Oct 2004 08:53

Why must the extended instruction set be disabled?

#1 Post by pizon » 13 Jun 2005 10:05

Q: Why must the extended instruction set on PIC18's that support it be disabled?

A: Some of the newer PIC18s (e.g. 2480, 2580, 4550 etc) support the 'Extended Instruction Set', which enables them to do the offset indexed addressing. However, that's not how mikroC (or any of the MikroE's compilers) has been designed to do. The explanation from Microchip's datasheets for relevant PICs says: When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0), or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instructions – may behave differently when the extended instruction set is enabled.


In other words, when the mikroC creates asm line

Code: Select all

MOVWF     0x5A
, it wants to store the value of WREG to the location 0x5A, and NOT to set the offset for indirect addressing.

This 'problem' can be solved in two ways:
  • 1. Disable the extended instruction set (e.g. for PIC18F2480, it's in the 4th config word - _CONFIG_4L: _XINST_OFF_4L); it can be done either from the compiler itself (<Project>-><Edit Project>), or in the PICFLASH tool.

    2. Leave the extended set enabled, but set the FSR2L and FSR2H to 0's at the beginning of your code; this will make the offset from the location 0x000000, which is the actual address stated. In this case you lose the FSR2 register pair.
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