so we decided to explain them using the examples, get 18F4550 datasheet and we can start:
- 18F4550 datasheet chapter 2.1:
You need to provide:
1) 48 MHz to USB module
2) Clock to CPU
- 18F4550 datasheet chapter 2.2.4 PLL FREQUENCY MULTIPLIER
It is designed to produce a fixed 96 MHz reference clock from a fixed 4 MHz input...
--- Example for 8MHz crystal on your board ---
1) Set _PLL_DIV2_1L.
PLL Prescaler (see Datasheet->Figure 2-1) will then divide 8MHz by 2 and produce 4MHz (needed on 96MHz PLL input).
2) Option 1
If you choose HSPLL oscillator (check _FOSC_HSPLL_HS_1H flag, uncheck _FOSC_INTOSC_HS_1H and _FOSC_HS_1H if checked)
In this case CPU will use 96MHz HSPLL divided by PLL Postscaller, set CPUDIV flags to choose the divider.
_CPUDIV_OSC1_PLL2_1L will divide 96MHz by 2 and CPU will get 48MHz [you need to set Clock field in EditProject to 48MHz]
...
_CPUDIV_OSC4_PLL6_1L will divide 96MHz by 6 and CPU will get 16MHz [you need to set Clock field in EditProject to 16MHz]
Note: PLLx part of the flag is relevant, ignore the OSCx part of the flag
Option 2
If you choose HS oscillator (check _FOSC_HS_1H flag, uncheck _FOSC_HSPLL_HS_1H and _FOSC_INTOSC_HS_1H if checked)
In this case CPU will use 8MHz HS divided by Oscillator Postscaller, set CPUDIV flags to choose the divider.
_CPUDIV_OSC1_PLL2_1L will divide 8MHz by 1 and CPU will get 8MHz [you need to set Clock field in EditProject to 8MHz]
...
_CPUDIV_OSC4_PLL6_1L will divide 8MHz by 4 and CPU will get 2MHz [you need to set Clock field in EditProject to 2MHz]
Note: OSCx part of the flag is relevant, ignore the PLLx part of the flag
--- Example for 20MHz crystal on your board ---
1) Set _PLL_DIV5_1L.
PLL Prescaler (see Datasheet->Figure 2-1) will then divide 20MHz by 5 and produce 4MHz (needed on 96MHz PLL input).
2) Option 1
If you choose HSPLL oscillator (check _FOSC_HSPLL_HS_1H flag, uncheck _FOSC_INTOSC_HS_1H and _FOSC_HS_1H if checked)
In this case CPU will use 96MHz HSPLL divided by PLL Postscaller, set CPUDIV flags to choose the divider.
_CPUDIV_OSC1_PLL2_1L will divide 96MHz by 2 and CPU will get 48MHz [you need to set Clock field in EditProject to 48MHz]
...
_CPUDIV_OSC4_PLL6_1L will divide 96MHz by 6 and CPU will get 16MHz [you need to set Clock field in EditProject to 16MHz]
Note: PLLx part of the flag is relevant, ignore the OSCx part of the flag
Option 2
If you choose HS oscillator (check _FOSC_HS_1H flag, uncheck _FOSC_HSPLL_HS_1H and _FOSC_INTOSC_HS_1H if checked)
In this case CPU will use 20MHz HS divided by Oscillator Postscaller, set CPUDIV flags to choose the divider.
_CPUDIV_OSC1_PLL2_1L will divide 20MHz by 1 and CPU will get 20MHz [you need to set Clock field in EditProject to 20MHz]
...
_CPUDIV_OSC4_PLL6_1L will divide 20MHz by 4 and CPU will get 5MHz [you need to set Clock field in EditProject to 5MHz]
Note: OSCx part of the flag is relevant, ignore the PLLx part of the flag
- Do not forget to check _USBDIV_2_1L to provide clock to USB module via PLL Prescaler and 96MHz PLL, this is not needed in the case
that you have 48MHz crystal so you can provide it directly to USB module.
mikroElektronika Team
