Advice on SPI Master-Slave Using Slave Select
Posted: 02 Jul 2022 02:06
I've just spent a day or two messing round with SPI comms and thought it may help someone else to explain what I've learnt?
The MCUs are 8bit PIC18F8722 with Fosc set to 40MHz.
The problems started when using the SLAVE SELECT (active low) control and eventually forced me to read the manual!
There must be a 'guard time' between the lowering of the SS and the start of data/clock and again after the last data/clock before the SS goes high.
The figures are quite specific but roughly 70Tcy to 80Tcy
The Xtal is 10MHz using 4XPLL. Fosc = 40MHz
So Tosc = 1000/40 = 25nS
1Tcy = 4*Tosc = 4*25 = 100nS
And allowing for a bit of capacitance I put guard delay into my code of 100Tcy = 100*100nS = 10uS
And suddenly everything worked!
I hope this helps someone?
Regards Bill Legge in Australia
The MCUs are 8bit PIC18F8722 with Fosc set to 40MHz.
The problems started when using the SLAVE SELECT (active low) control and eventually forced me to read the manual!
There must be a 'guard time' between the lowering of the SS and the start of data/clock and again after the last data/clock before the SS goes high.
The figures are quite specific but roughly 70Tcy to 80Tcy
The Xtal is 10MHz using 4XPLL. Fosc = 40MHz
So Tosc = 1000/40 = 25nS
1Tcy = 4*Tosc = 4*25 = 100nS
And allowing for a bit of capacitance I put guard delay into my code of 100Tcy = 100*100nS = 10uS
And suddenly everything worked!
I hope this helps someone?
Regards Bill Legge in Australia
