//UPDATED ON 24 JULY 2009/////////
jozef333@ymail.com/////////////////////////////////////////////////////////////
///////visit
http://ahaanow.us.to/////////////////// ... //////////
///////////////////////////////////////////////////////////////////////////////
// CC1100 STROBE, CONTROL AND STATUS REGSITER//////////////////////////////////
#define CC1100_IOCFG2 0x00 // GDO2 output pin configuration
#define CC1100_IOCFG1 0x01 // GDO1 output pin configuration
#define CC1100_IOCFG0 0x02 // GDO0 output pin configuration
#define CC1100_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CC1100_SYNC1 0x04 // Sync word, high byte
#define CC1100_SYNC0 0x05 // Sync word, low byte
#define CC1100_PKTLEN 0x06 // Packet length
#define CC1100_PKTCTRL1 0x07 // Packet automation control
#define CC1100_PKTCTRL0 0x08 // Packet automation control
#define CC1100_ADDR 0x09 // Device address
#define CC1100_CHANNR 0x0A // Channel number
#define CC1100_FSCTRL1 0x0B // Frequency synthesizer control
#define CC1100_FSCTRL0 0x0C // Frequency synthesizer control
#define CC1100_FREQ2 0x0D // Frequency control word, high byte
#define CC1100_FREQ1 0x0E // Frequency control word, middle byte
#define CC1100_FREQ0 0x0F // Frequency control word, low byte
#define CC1100_MDMCFG4 0x10 // Modem configuration
#define CC1100_MDMCFG3 0x11 // Modem configuration
#define CC1100_MDMCFG2 0x12 // Modem configuration
#define CC1100_MDMCFG1 0x13 // Modem configuration
#define CC1100_MDMCFG0 0x14 // Modem configuration
#define CC1100_DEVIATN 0x15 // Modem deviation setting
#define CC1100_MCSM2 0x16// Main Radio Control State Machine configuration
#define CC1100_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CC1100_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CC1100_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CC1100_BSCFG 0x1A // Bit Synchronization configuration
#define CC1100_AGCCTRL2 0x1B // AGC control
#define CC1100_AGCCTRL1 0x1C // AGC control
#define CC1100_AGCCTRL0 0x1D // AGC control
#define CC1100_WOREVT1 0x1E // High byte Event 0 timeout
#define CC1100_WOREVT0 0x1F // Low byte Event 0 timeout
#define CC1100_WORCTRL 0x20 // Wake On Radio control
#define CC1100_FREND1 0x21 // Front end RX configuration
#define CC1100_FREND0 0x22 // Front end TX configuration
#define CC1100_FSCAL3 0x23 // Frequency synthesizer calibration
#define CC1100_FSCAL2 0x24 // Frequency synthesizer calibration
#define CC1100_FSCAL1 0x25 // Frequency synthesizer calibration
#define CC1100_FSCAL0 0x26 // Frequency synthesizer calibration
#define CC1100_RCCTRL1 0x27 // RC oscillator configuration
#define CC1100_RCCTRL0 0x28 // RC oscillator configuration
#define CC1100_FSTEST 0x29 // Frequency synthesizer calibration control
#define CC1100_PTEST 0x2A // Production test
#define CC1100_AGCTEST 0x2B // AGC test
#define CC1100_TEST2 0x2C // Various test settings
#define CC1100_TEST1 0x2D // Various test settings
#define CC1100_TEST0 0x2E // Various test settings
// Strobe commands/////////////////////////////////////////////////////////////
#define CC1100_SRES 0x30 // Reset chip.
#define CC1100_SFSTXON 0x31 // Enable and calibrate frequency synthesizer
//(if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CC1100_SXOFF 0x32 // Turn off crystal oscillator.
#define CC1100_SCAL 0x33 // Calibrate frequency synthesizer
//and turn it off
// (enables quick start).
#define CC1100_SRX 0x34 // Enable RX. Perform calibration first
// if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CC1100_STX 0x35 //In IDLE state:Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CC1100_SIDLE 0x36//Exit RX/TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CC1100_SAFC 0x37// Perform AFC adjustment of the frequency synthesizer
#define CC1100_SWOR 0x38// Start automatic RX polling sequence (Wake-on-Radio)
#define CC1100_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CC1100_SFRX 0x3A // Flush the RX FIFO buffer.
#define CC1100_SFTX 0x3B // Flush the TX FIFO buffer.
#define CC1100_SWORRST 0x3C // Reset real time clock.
#define CC1100_SNOP 0x3D//No operation.May be used to pad strobe commandsto two
// bytes for simpler software.
#define CC1100_PARTNUM 0x30
#define CC1100_VERSION 0x31
#define CC1100_FREQEST 0x32
#define CC1100_LQI 0x33
#define CC1100_RSSI 0x34
#define CC1100_MARCSTATE 0x35
#define CC1100_WORTIME1 0x36
#define CC1100_WORTIME0 0x37
#define CC1100_PKTSTATUS 0x38
#define CC1100_VCO_VC_DAC 0x39
#define CC1100_TXBYTES 0x3A
#define CC1100_RXBYTES 0x3B
#define CC1100_PATABLE 0x3E
#define CC1100_TXFIFO 0x3F
#define CC1100_RXFIFO 0x3F
#define CRC_OK 0x80
///////////////////////////////////////////////////////////
///SPI Based CC1100 Tranceiver module//////////////////////////////////////////
#define WRITE_SINGLE 0x00 //
#define WRITE_BURST 0x40 // || R/W- , B , AD5-AD0 ||
#define READ_SINGLE 0x80 //
#define READ_BURST 0xC0 //
/////////////////////////////
#define SCK PORTC.F3 //is connected to SCLK of CC1100
#define SI PORTC.F4 //is connected to SO of CC1100
#define SO PORTC.F5 //is connected to SI of CC1100
#define CS PORTC.F6 //is connected to CSn of CC1100
#define TE PORTC.F7 //is connected to TE of CC1100
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
unsigned char paTable[] = {0x60};//{0xC0, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F };//
unsigned char txBuffer[] = {9, 1, 0x01,0x02,0x03,0x04,0x05,0x06,0x07};
//{20, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
// 14, 15, 16, 17, 18, 19};//{2, 1, 0x01};
unsigned char rxBuffer[31];
//unsigned char dpybuffer[10]={0x11,0xF9,0x23,0x61,0xC9,0x45,0x05,0xF1,0x01,0x41};
unsigned char rfstate;
////////SPI is implemented through software here
////volatile char SPI_RX_Buffer; // receives data as in SSPSR shift register
//volatile char SPI_TX_Buffer; // tx data as in SSPSR shift register
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
////PIC 16F877A///SPI FUNCTIONS///////////////
///////////////////////////////////////////////////////////////////////////////
/////////////////AD_SPI_init()/////////////////////////////////////////////////
//Initialze the SPI peripheral/////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
unsigned char AD_SPI_write(unsigned char content)
{
unsigned char status=0x00;
unsigned char value=0x00,i;
SCK=0; //In IDLE clock should be 0
for(i=0;i<8;i++)
{
value=(content & 0x80);
if(value!=0x00) //checking each bits
{
//SCK=0;
SO=1;
}
else
{
//SCK=0;
SO=0;
}
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
SCK=1; //clock from L to H
asm nop;
asm nop;
asm nop;
asm nop;
content=content<<1; //shifting for next bit
status=status<<1;
if(SI==1)
{
status=status|0x01;
}
else if(SI==0)
{
status=status&0xFE;
}
asm nop;
asm nop;
asm nop;
asm nop;
SCK=0;
}
SCK=0;
return status;
}
//////////////////////////////////////////////////////////////////////////////
unsigned char AD_SPI_read(void)
{
unsigned char i=0;
unsigned char content=0x00;
SCK=0;
for(i=0;i<8;i++)
{
content=content<<1;
SCK=1;
if(SI==1)
{
content=content|0x01;
}
else if(SI=0)
{
content=content&0xFE;
}
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
asm nop;
SCK=0;
asm nop;
asm nop;
asm nop;
asm nop;
}
SCK=0;
return content;
}
///////////////////////////////////////////////////////////////////////////////
////////////////////////END of SPI Functions///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
////////////////////////CC1100 Special Routines////////////////////////////////
//unsigned char AD_SPI_read(void) //100ns btw each read/write
//unsigned char AD_SPI_write(unsigned char)
// unsigned char AD_CC1100_read_REG(unsigned char address)
// AD_CC1100_write_REG
// AD_CC1100_read_STATUSREG
// AD_CC1100_command_STROBE
// AD_CC1100_read_BURST
// AD_CC1100_write_BURST
// AD_CC1100_RxTxStatus
//
// AD_CC1100_PWR_RST
///////////////////////////////////////////////////////////////////////////////
unsigned char AD_CC1100_read_REG(unsigned char address)
{
unsigned char value;
address|=READ_SINGLE;
CS=1;
SCK=0; //jst to be sure
CS=0;
while(SI); //Wait for SI to become zero
AD_SPI_write(address);
Delay_us(10); //A min 100ns delay bw each access
value=AD_SPI_read();
SCK=0;
SI=1;
SO=0; //default position
CS=1; //
return value;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_write_REG(unsigned char address, unsigned char value)
{
//unsigned char value;
CS=1;
SCK=0;
SCK=1;
SCK=0;
SCK=1;
SCK=0;
address|=WRITE_SINGLE;
CS=0;
while(SI);
AD_SPI_write(address);
Delay_us(10);
AD_SPI_write(value);
SCK=0;
SO=0;
CS=1;
}
///////////////////////////////////////////////////////////////////////////////
// No burst mde available for status read (readonly)///////////////////////////
unsigned char AD_CC1100_read_STATUSREG(unsigned char address)
{
unsigned char value;
address|=READ_BURST; ///STATUS reg frm 0x30-0x3D B=1-status,B=0-command strobe
CS=1;
SCK=0;
CS=0;
while(SI);
AD_SPI_write(address);
Delay_us(10);
value=AD_SPI_read();
SCK=0;
SO=0;
CS=1;
return value;
}
///////////////////////////////////////////////////////////////////////////////
// Do not use for SRES strobes...check whether SO become low......
unsigned char AD_CC1100_command_STROBE(unsigned char value) // write- only
{
unsigned char status=0;
CS=1;
SCK=0;
SO=0;
CS=0;
while(SI);
status=AD_SPI_write(value);
CS=1;
SCK=0;
SO=0;
return status;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_read_BURST(unsigned char address, unsigned char *buffer,
unsigned char count)
{
unsigned int j=0;
unsigned char value;
address|=READ_BURST;
CS=1;
SCK=0;
CS=0;
while(SI);
AD_SPI_write(address);
Delay_us(10);
for(j=0;j<count;j++)
{
value=AD_SPI_read();
buffer[j]=value;
Delay_us(10);
}
CS=1;
SCK=0;
SO=0;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_write_BURST(unsigned char address, unsigned char *buffer,
unsigned char count)
{
unsigned int j=0;
unsigned char value;
address|=WRITE_BURST;
CS=1;
SCK=0;
CS=0;
while(SI);
AD_SPI_write(address);
Delay_us(10);
for(j=0;j<count;j++)
{
value=buffer[j];
AD_SPI_write(value);
Delay_us(10);
}
CS=1;
SCK=0;
SO=0;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_RfSendPacket(unsigned char *txBuffer, unsigned char size)
{
unsigned char test=0x00;
// unsigned char i=0Xff;
AD_CC1100_command_STROBE(CC1100_SFTX); //flush TX Fifo
//Delay_ms(1);
AD_CC1100_write_BURST(CC1100_TXFIFO, *txBuffer, size);
//Delay_ms(1);
if(((AD_CC1100_read_STATUSREG(CC1100_TXBYTES))& 0x7F)==0x03)
{
PORTA.F2=1;
}
AD_CC1100_command_STROBE(CC1100_STX); //Enable TX if in IDLE mode
//Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
//when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
while(((AD_CC1100_read_STATUSREG(CC1100_TXBYTES))& 0x7F)!=0x00)
{
Delay_us(5);
PORTA.F0=1;
}
/*
while((AD_CC1100_read_STATUSREG(CC1100_PKTSTATUS) & 0x01)==0x01)
{
PORTA.F3=1; //sync detected
Delay_us(5);
}
if(((AD_CC1100_command_STROBE(CC1100_SNOP)) & 0x70)==0x70)
{
PORTA.F1=1; //overflow occured;
AD_CC1100_command_STROBE(CC1100_SFTX);//clear fifo
}
if(((AD_CC1100_command_STROBE(CC1100_SNOP)) & 0x0F)==0x0F)
{
//finished FIFO empty
PORTA.F2=~PORTA.F2;
//so end tx
AD_CC1100_command_STROBE(CC1100_SIDLE);
} */
// AD_CC1100_command_STROBE(CC1100_SIDLE);//idele
// AD_CC1100_command_STROBE(CC1100_SIDLE);//idele
PORTA.F1=~PORTA.F1;
//Delay_ms(5);
//while(1);
// AD_CC1100_command_STROBE(CC1100_SFTX); //flush TX Fifo
//AD_CC1100_command_STROBE(CC1100_SIDLE);
// TMR0=0; T0IF=0; //can be used to speed up
/*while(((AD_CC1100_read_STATUSREG(CC1100_TXBYTES))& 0x7F)!=0x00) //wait untill txmision over
{
//PORTA.F2=~PORTA.F2;
//PORTA=test;
Delay_ms(100);
if((AD_CC1100_read_STATUSREG(CC1100_TXBYTES)&0x80)==0x00)
{
//PORTA.F1=~PORTA.F1;
Delay_ms(100);
//underflow so do SFTX
AD_CC1100_command_STROBE(CC1100_SFTX); //flush TX Fifo
}
} */
//{
//PORTA.F0=~PORTA.F0;//1; //lightup
// Delay_ms(100);
// if(T0IF) return ; //
// }
//PORTA.F0=1; //lightup
//Delay_ms(500);
//PORTA.F0=0; //led OFF
//return ;
}
///////////////////////////////////////////////////////////////////////////////
unsigned char AD_CC1100_RfReceivePacket(unsigned char *rxBuffer,
unsigned char length)
{
unsigned char status[2];
unsigned char packetLength;
//wait till sync received GDO set
//wait for end of packet GD0 Cleared
packetLength=AD_CC1100_read_REG(CC1100_RXFIFO); //read first byte in RXFIFO
if(packetLength <= length) //STORE IT TO LENGTH
{
length = packetLength;
// AD_CC1100_read_BURST(CC1100_RXFIFO,rxBuffer,packetLength);
//AD_CC1100_read_BURST(CC1100_RXFIFO, status, 2);//[RSSI] [CRC OK-7,LQI-6-0].
}
else
{
length = packetLength;
AD_CC1100_command_STROBE(CC1100_SIDLE); //change to IDLE
AD_CC1100_command_STROBE(CC1100_SFRX); //FLUSH FIFO
}
if(packetLength==9)
{
PORTA.F0=1;
PORTA.F2=0;
PORTA.F3=0;
}
//PORTA=packetLength;
//
//if(rxbuffer[2]==0x01)
//{
// PORTA.F0=~PORTA.F0; //success!!!!
// while(1);
//}
//
// PORTA.F1=0;
// PORTA.F2=0;
// PORTA.F3=0;
}
///////////////////////////////////////////////////////////////////////////////
unsigned char AD_CC1100_RxTxStatus(void)
{
// unsigned char RxTxstatus;
unsigned char value;
CS=0;
while (SI);
AD_SPI_write(CC1100_SNOP);
value=AD_SPI_read();
SCK=0;
SO=0;
CS=1;
return value;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_PWR_RST(void)
{
unsigned char i;
AD_CC1100_command_STROBE(CC1100_SIDLE);
CS=1;
for(i=0;i<5;i++);
CS=0;
for(i=0;i<5;i++);
CS=1;
for(i=0;i<200;i++);
CS=0;
while(SI);
AD_CC1100_command_STROBE(CC1100_SRES);
CS=1;
SCK=0;
SO=0;
}
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////TX/RX SECTION///////////////////////////////////
void AD_CC1100_Tx(void)
{
unsigned char i;
// AD_CC1100_write_REG(0x3E,0xC0); //POWER=10DBM
PORTA.F2=0; //
PORTA.F3=0; ///
AD_CC1100_write_REG(CC1100_FREND0, 0x10);//Front End TX Config (GIVEN BY RF STUDIO)
Delay_ms(5);
for(i=0;i<4;i++)
{
AD_CC1100_RfSendPacket(txBuffer, sizeof(txBuffer));
Delay_ms(5);
}
// AD_CC1100_write_REG(0x3E,0x7f); //POWER=0DBM
AD_CC1100_write_REG(CC1100_FREND0, 0x11); //change TX config
Delay_ms(5);
AD_CC1100_RfSendPacket(txBuffer, sizeof(txBuffer));
Delay_ms(5);
//PORTC=0xFF;
}
///////////////////////////////////////////////////////////////////////////////
unsigned char AD_CC1100_Rx(void)
{
unsigned char length,i;
length = sizeof(rxBuffer);
if (AD_CC1100_RfReceivePacket(rxBuffer, length))
{
i=rxBuffer[0];
//PORTC=dpybuffer[i];
//LED2=LED_ON;
//LED1=LED_OFF;
return 1;
}
else return 0;
}
///////////////////////////////////////////////////////////////////////////////
void AD_CC1100_WriteRfSettings(void)
{
AD_CC1100_write_REG(CC1100_FSCTRL1, 0x0A); // Desired IF freq to employ in RX
AD_CC1100_write_REG(CC1100_FSCTRL0, 0x00); // Freq offset added to base freq
AD_CC1100_write_REG(CC1100_FREQ2, 0x10); // base freq for freq synthesizer
AD_CC1100_write_REG(CC1100_FREQ1, 0xA7); //cont freq2 reg....page68
AD_CC1100_write_REG(CC1100_FREQ0, 0x62); //do
AD_CC1100_write_REG(CC1100_MDMCFG4, 0x2D); // p69
AD_CC1100_write_REG(CC1100_MDMCFG3, 0x3B); //
AD_CC1100_write_REG(CC1100_MDMCFG2, 0x73); // modulation type, manc enc, sync wrd qualifier
AD_CC1100_write_REG(CC1100_MDMCFG1, 0x22); //FEC, PREamble, CH spacing
AD_CC1100_write_REG(CC1100_MDMCFG0, 0xF8); // Channel spacing
AD_CC1100_write_REG(CC1100_CHANNR, 0x00); // channel No
AD_CC1100_write_REG(CC1100_DEVIATN, 0x00); ///when in msk -deviation
AD_CC1100_write_REG(CC1100_FREND1, 0xB6);
AD_CC1100_write_REG(CC1100_FREND0, 0x10);
AD_CC1100_write_REG(CC1100_MCSM0, 0x18); //radio control machine state // auto calibrate
AD_CC1100_write_REG(CC1100_FOCCFG, 0x1D);
AD_CC1100_write_REG(CC1100_BSCFG, 0x1C);
AD_CC1100_write_REG(CC1100_AGCCTRL2, 0xC7);
AD_CC1100_write_REG(CC1100_AGCCTRL1, 0x00);
AD_CC1100_write_REG(CC1100_AGCCTRL0, 0xB0);
AD_CC1100_write_REG(CC1100_FSCAL3, 0xEA);
AD_CC1100_write_REG(CC1100_FSCAL2, 0x2A);
AD_CC1100_write_REG(CC1100_FSCAL1, 0x00);
AD_CC1100_write_REG(CC1100_FSCAL0, 0x1F);
AD_CC1100_write_REG(CC1100_FSTEST, 0x59);
AD_CC1100_write_REG(CC1100_TEST2, 0x88);
AD_CC1100_write_REG(CC1100_TEST1, 0x31);
AD_CC1100_write_REG(CC1100_TEST0, 0x09);
AD_CC1100_write_REG(CC1100_FIFOTHR, 0x07);
AD_CC1100_write_REG(CC1100_IOCFG2, 0x29); //WOR_EVNT0 ??? //Default 0x29 Chip ready
AD_CC1100_write_REG(CC1100_IOCFG0, 0x06); // Assert when sync wrd sent //Default 0x3F osc/192....
AD_CC1100_write_REG(CC1100_PKTCTRL1, 0x04); // 2 stst bytes appended, RSSI, LQI and CRC ok
AD_CC1100_write_REG(CC1100_PKTCTRL0, 0x05); //whitening off, crc en, var packet length mode
AD_CC1100_write_REG(CC1100_ADDR, 0x00); //ADDRESS for Packet filteration
AD_CC1100_write_REG(CC1100_PKTLEN, 0xFF);
}
//////////////////TESTED FUNCTONS//////////////////////////////////////////////
unsigned char AD_CC1100_POWERUP(void)
{
unsigned status=0xFF; // For debug to be deleated
CS=1; //default state
SCK=1;
SO=0;
CS=0;
Delay_ms(5);
CS=1;
Delay_ms(5);
CS=0;
CS=1;
status=AD_CC1100_command_STROBE(CC1100_SRES);
//status=status>>3; // to check if idle
//PORTA=status; // working
}
///////////////////EOF TESTED FUNCTIONS////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////EOF CC1100 Routines///////////////////////////////
///////////////////////////////////////////////////////////////////////////////
void main()
{
short take,take1,take2,take3,take4, buffer;
unsigned char test;
unsigned char status=0xFF;
TRISC.F3=0;//SCK output port
TRISC.F4=1;//SI input port
TRISC.F5=0;//SDO output
TRISC.F6=0;//CS output
TRISC.F7=0;//TE output
///
PORTA=0x00;
TRISA=0x00;
ADCON1=0x07;
//
CS=1; //default state
SCK=0;
//SI=1; // do
//SO=0;
/////////////////////////
AD_CC1100_POWERUP(); //Powering UP the Module
Delay_ms(1);
AD_CC1100_WriteRfSettings();
AD_CC1100_write_BURST(CC1100_PATABLE, paTable, sizeof(paTable));
TE=1; //enable amp
while(1)
{
AD_CC1100_RfSendPacket(txBuffer, sizeof(txbuffer));
//test=AD_CC1100_read_REG(CC1100_PATABLE);
//PORTA=0xFF;
//PORTA=test>>4;
}
//while(1);
/*while(1)
{
AD_CC1100_RfSendPacket(txBuffer, sizeof(txbuffer));
Delay_ms(100);
}*/
//status=AD_CC1100_read_STATUSREG(0x31); //read version
//PORTA=status;
////////////////////////////
// while(1)
// {
//
// }
//TE=1;
//AD_CC1100_PWR_RST(); ///Perform power ON reset
//status=AD_CC1100_command_STROBE(CC1100_SNOP);
//If reset sucess then should be in idle state
/*
AD_CC1100_WriteRfSettings();
AD_CC1100_write_BURST(CC1100_PATABLE, paTable, sizeof(paTable));
PORTA=0x00;
TRISA=0x00;
ADCON1=0x07;
//AD_SPI_read();
//AD_CC1100_PWR_RST();
while(1)
{
// AD_SPI_read(0xA);
// PORTA.F0=~PORTA.F0;
Delay_ms(500);
rfstate=AD_CC1100_read_REG(CC1100_MARCSTATE);//Main Radio Control State Machine State
if((rfstate & 0x1F)==0x00) // if in sleep mode
{
PORTA.F2=1;
PORTA.F3=1;
///LED1=LED_OFF;
//LED2=LED_OFF;
AD_CC1100_PWR_RST(); //perform power reset
AD_CC1100_WriteRfSettings(); //load settings
}
AD_CC1100_Tx();//this data in buffer is txed txBuffer[] = {2, 1, 0x01};
} */
}
////////////////////////////////
/*
//old rf setting back up
void AD_CC1100_WriteRfSettings(void)
{
AD_CC1100_write_REG(CC1100_FSCTRL1, 0x0C); // Desired IF freq to employ in RX
AD_CC1100_write_REG(CC1100_FSCTRL0, 0x00); // Freq offset added to base freq
AD_CC1100_write_REG(CC1100_FREQ2, 0x10); // base freq for freq synthesizer
AD_CC1100_write_REG(CC1100_FREQ1, 0xB0); //cont freq2 reg....page68
AD_CC1100_write_REG(CC1100_FREQ0, 0x71); //do
AD_CC1100_write_REG(CC1100_MDMCFG4, 0xC6); // p69
AD_CC1100_write_REG(CC1100_MDMCFG3, 0x83); //
AD_CC1100_write_REG(CC1100_MDMCFG2, 0x02); // modulation type, manc enc, sync wrd qualifier
AD_CC1100_write_REG(CC1100_MDMCFG1, 0x22); //FEC, PREamble, CH spacing
AD_CC1100_write_REG(CC1100_MDMCFG0, 0xF8); // Channel spacing
AD_CC1100_write_REG(CC1100_CHANNR, 0x00); // channel No
AD_CC1100_write_REG(CC1100_DEVIATN, 0x30); ///when in msk -deviation
AD_CC1100_write_REG(CC1100_FREND1, 0x56);
AD_CC1100_write_REG(CC1100_FREND0, 0x10);
AD_CC1100_write_REG(CC1100_MCSM0, 0x18); //radio control machine state // auto calibrate
AD_CC1100_write_REG(CC1100_FOCCFG, 0x15);
AD_CC1100_write_REG(CC1100_BSCFG, 0x6C);
AD_CC1100_write_REG(CC1100_AGCCTRL2, 0x03);
AD_CC1100_write_REG(CC1100_AGCCTRL0, 0x91);
AD_CC1100_write_REG(CC1100_FSCAL3, 0xA9);
AD_CC1100_write_REG(CC1100_FSCAL2, 0x2A);
AD_CC1100_write_REG(CC1100_FSCAL0, 0x0D);
AD_CC1100_write_REG(CC1100_FSTEST, 0x59);
AD_CC1100_write_REG(CC1100_TEST2, 0x86);
AD_CC1100_write_REG(CC1100_TEST1, 0x3D);
AD_CC1100_write_REG(CC1100_TEST0, 0x09);
AD_CC1100_write_REG(CC1100_IOCFG2, 0x24); //WOR_EVNT0 ??? //Default 0x29 Chip ready
AD_CC1100_write_REG(CC1100_IOCFG0, 0x06); // Assert when sync wrd sent //Default 0x3F osc/192....
AD_CC1100_write_REG(CC1100_PKTCTRL1, 0x04); // 2 stst bytes appended, RSSI, LQI and CRC ok
AD_CC1100_write_REG(CC1100_PKTCTRL0, 0x05); //whitening off, crc en, var packet length mode
AD_CC1100_write_REG(CC1100_ADDR, 0x00); //ADDRESS for Packet filteration
AD_CC1100_write_REG(CC1100_PKTLEN, 0xFF);
}*/