Programming dsPIC MCU in PASCAL

Chapter5: Input Capture

Introduction

The input capture module has the task of capturing the curent value of the timer counter upon an input event. This module is mainly used for the frequency or time period measurements and pulse measurements (e.g. mean count rate measurement). Microcontroller dsPIC30F4013 contains 4 input capture modules, whereas dsPIC30F6014A contains 8 input capture modules.

The input capture module has multiple operatig modes selectable via the ICxCON register (control bit ICM<2:0>):

• Select by external input signal mode,
• Interrupt by external input signal mode.

The input capture module contains a four-level FIFO buffer. By setting the control bits a user can select the number of captures from the counter before the input capture module generates an interrupt request.

Fig. 5-1 Functional diagram of the inpuit capture module

5.1 External signal capture input mode

In the family of dsPIC30F microcontrollers the select by external input signal mode implies selecting the value from the TMR2 or TMR3 counter depending on the external input signal at pin ICx. The capture can be carried out depending on the external input signal:

• on every falling edge of input signal applied at the ICx pin,
• on every rising edge of input signal applied at the ICx pin,
• on every risinig and every falling edge of input signal applied at the ICx pin,
• on every fourth rising edge of input signal applied at the ICx pin,
• on every 16th rising edge of input signal applied at the ICx pin,

The selection of the input captue mode is carried out by setting the control bits ICM<2:0> in the register ICxCON<2:0>. Also, by setting the control bits ICM<2:0> the reduction ratio in the prescaler 1, 4 , or 16 is set.

NOTE: The counter register of the input capture module is cleared upon RESET or switch off.

5.1.1 Simple capture mode

The simple capture mode, or the mode of simple capture, is the mode of the input capture module when the capture is done on every rising edge or every falling edge of the external input signal at the input pin ICx. In this mode the logic of the input capture module detects the change of the logical level at the input pin ICx, synchronizes the change with the phase of the internal clock, captures the value of the counter TMR2 or TMR3 and puts it into the FIFO buffer memory. The prescaler operates wth the ratio 1:1, i.e. without reduction.

Since the input capture module comprises a four-level FIFO buffer, by setting the control bit ICI<1:0> (ICxCON<6:5>) it is possible to select the number of captures before an interrupt is generated. In this way capturing of fast external signals is made possible because while the counter values are captured and put into the FIFO buffer, it is possible to read previous values in the buffer and transfer them to the data memory.

Selection of the counter of the timer module which is to be captured is done by setting the control bit ICTMR (ICxCON<7>). It is possible to select the 16-bit counters TMR2 (ICTMR=1) or TMR3 (ICTMR=0).

Example:

This example demostrates the operation of the input capture module in the simple capture mode. The value of the counter of timer2 TMR2 is captured on the falling edge of the IC1 signal (pin RD8). The captured value is put to portB.

program Input_Capture_test;
procedure Input1CaptureInt; org $16;
begin
  LATB   := IC1BUF; //Read captured values and put to portB
  IFS0.1 := 0;      //Clear bit IC1IF (IFS<1>)
end;

begin
  TRISB  := 0;            //PORTB is output
  LATB   := 0;            //Initial value at PORTB
  TRISD  := $0100;        //Select pin IC1 (RD8) as input
  IPC0   := IPC0 or $0010; //Interrupt priority level IC1IP<2:0> = 1
  IEC0   := IEC0 or $0002; //Interrupt Input Compare module enable
  PR2    := $FFFF; //PR2 register at maximum, timer2 free-running
  T2CON  := $8030; //Timer 2 operates with prescaler 1:256 and internal clock
  IC1CON := $0082; //Configuration of Input  Capture module 1, selected TMR2,
                   //capture on falling edge
while TRUE do      //Endless loop
  nop;
end.

During interrupt routine clearing the interrupt Input Capture module request flag is mandatory and the captured value is read form the FIFO buffer. In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535. Input Capture module 1 is configured to capture values of timer 2 on falling edge of the signal at IC1 pin.

5.1.2 Prescaler capture mode

In this mode of operation of the input capture module the external signal is prescaled by the ratio 1:4 or 1:16 by setting the control bit ICM<2:0> to the values 100 or 101 respectively. In this way it is possible that the input capture module captures total value of the counter TMR2 or TMR3 for 4 or 16 periods of the external signal at the pin ICx. This is the way of measuring mean count rate by averaging 4 or 16 periods of an extarnal input signal.

By setting the control bit IC1<1:0> (ICxCON<6:5>) it is also possible, like in the simple capture mode, to select the number of captures after which an interrupt request is generated.

The selection of the timer module which is to be sampled is done by setting the control bit ICTMR (ICxCON<7>).

NOTE: If the time base is incremented by each instruction cycle, then the result of capturing will be available in the FIFO buffer one or two instruction cycles after the synchronous change at the input pin ICx, in phase with the internal clock of the microcontroller. An example of setting the captured value delayed by 1 or 2 instruction cycles TCY is shown in Fig. 5-2.

Attention!
Before the operational mode is changed the input capture module should be turned off, i.e. the control bits ICM<2:0> cleared. If the mode is changed without clearing ICM<2:0>, there is a resudual content in the prescaler counter which leads to the premature sampling and interrupt request generation.

Example:

This example demonstrates the operation of the input capture module in the prescaler capture mode. The example shows capturing the values of the timer2 counter TMR2 on each fourth rising edge if the IC1 signal (pin RD8). The captured value is put to portB.

program Input_Capture_test2;
procedure Input1CaptureInt; org $16;
begin
  LATB   := IC1BUF;  //Read captured value and put to PORTB
  IFS0.1 := 0;       //Clear IC1IF bit (IFS<1>)
end;

begin
  TRISB  := 0;            //PORTB iz output
  LATB   := 0;            //Initial value at PORTB
  TRISD  := $0100;        //Select pin IC1 (RD8) as input
  IPC0   := IPC0 or $0010; //Interrupt priority level is
  IEC0   := IEC0 or $0002; //Interrupt Input Capture module 1 enable
  PR2    := $FFFF;        //PR2 register at maximum, timer2 free-running
  T2CON  := $8030;        //Timer 2 operates with prescaler 1:256 and internal clock
  IC1CON := $0084;        //Configuration of Input  Capture module 1, selected TMR2,
                          //capture on each 4th rising edge
while TRUE do             //Endless loop
  nop;
end.

During interrupt routine clearing the interrupt Input Capture module request flag is mandatory and the captured value is read form the FIFO buffer. In setting timer2 the preset register PR2 is set at the maximum value in order to ensure operation of the timer in the free-running mode over the full range of values, from 0 to 65535. Input Compaer module 1 is configured to capture values of timer 2 on each fourth rising edge of the signal at IC1 pin.

5.1.3 Edge detection mode

Capturing the value of TMR2 or TMR3 counter can be done on every rising and every falling edge of the external input signal applied to the ICx pin. The edge detection mode is selected by setting the ICM<2:0> (ICxCON<2:0>) control bits to 001. In this mode the prescaler counter can not be used. The input capture module interrupt request is generated on every rising and every falling edge (ICxIF bit is set). It not possible to generate an interrupt request after 2, 3, or 4 captures by setting the control bits ICI<1:0> (ICxCON<6:5>) because in this mode they are ignored. Every capture event generates an interrupt. As a consequence no overflow of the FIFO buffer is possible.

NOTE: If the time base is incremented by each instruction cycle, then the result of capturing will be available in the FIFO buffer one or two instruction cycles after the synchronous change at the input pin ICx, in phase with the internal clock of the microcontroller. An example of setting the captured value delayed by 1 or 2 instruction cycles TCY is shown in Fig. 5-2.

Fig. 5-2 An example of setting the captured value delayed by 1 or 2 instruction cycles TCY

Reading data from FIFO buffer – Each input capture module comprises a four-level (16-bit) FIFO buffer for accomodation of the captures. The access to the captures in the FIFO buffer is via the ICxBUF register. In addition, there are two status flags ICBNE (ICxCON<3>) and ICOV (ICxCON<4>) defining the status of the FIFO buffer. The ICBNE status flag denotes that the FIFO buffer is not empty. This flag is cleared by hardware when the last word is read from the FIFO buffer or during the reset of the input capture module by setting the control bits ICM<2:0> to value 000. ICBNE is also reset during RESET.

The other status flag ICOV denotes the state of overflow of the FIFO buffer, i.e. when after four captures which have not been transferred to the data memory the fifith capture is being put in. No interrupt request is generated then, the ICOV bit is set and the values of the five captures and all subsequent captures are ignored. Clearing of this bit is done by hardware upon reading of all four captures from the FIFO buffer, or by resetting of the input capture module. Also, the microcontroller RESET clears this flag.

5.2 External signal interrupt mode

The input pins of the input capture module can be used as additional external interrupt sources if the input capture module is configured for operation in the external signal interrupt mode. This accomplished when the configuration bits ICM<2:0> are set to 111. Then, the input pins ICx on rising edge generate an interrupt request ICxIF. If the interrupt enable bit ICxIE is set and the interrupt priority level ICxIP<2:0>is defined, the microcontroller enters an interrupt.

NOTE: Inorder that the input capture module configured to operate in the external signal interrupt mode could operate in this mode, it is necssary to clear the control bits ICI<1:0> (ICxCON<6:5>= 0). Then, the interrupt is generated independently of the reading of the FIFO buffer. Also, the status bit ICOV has to be cleared.

The input capture module is very often used by the UART module for autodetection of the baud rate. In the autobaud mode the UART module is configured as follows: the control bit ABAUD (UxMODE<5>) is set i.e. the UART RX pin is internally connected to the input capture module input. and the ICx pin is disconnected from the rest of the input capture module.The baud rate is measured by measuring the the width of the START bit when a NULL character is received. Care should be taken that the input capture module is configured for the edge detection mode. For each microcontroller of the family dsPIC30F the input capture module assignment for each UART has been defined.

5.3 Input capture operation in SLEEP and IDLE modes

Input capture operation in SLEEP mode – In SLEEP mode, the system clock is disabled, i.e. the input capture module can only function as an external interrupt source. This mode is enabled by setting control bits ICM<2:0> to 111. A rising edge on the ICx input pin will generate an input capture module interrupt. If the interrupt is enabled for this input pin, the microcontroller will wake-up from SLEEP.

In the event the input capture module has been configured for a mode other than ICM<2:0>=111 and the microcontroller enters the SLEEP mode, no external signal, rising or falling, can generate a wake-up condition from SLEEP.

Input capture operation in IDLE mode – Operation of the input capture module in IDLE mode is specified by the control bit ICSIDL (ICxCON<13>). If ICSIDL= 0, the module will continue operation in IDLE mode with full functionality in all the above mentioned modes. The prescaler is fully functional in this mode.

If ICSIDL=1, the module will stop in IDLE mode. Then, the input capture module can operate only in the external signal interrupt mode, i.e. the control bits ICM<2:0>=111. A rising edge on the ICx input pin will generate an input capture module interrupt. If the interrupt is enabled for this input pin, the microcontroller will wake-up from IDLE state.

In the event the input capture module has been configured for a different mode and the microcontroller enters the IDLE mode with the control bit ICSIDL is set, no external signal, rising or falling, can generate a wake-up condition from IDLE state.

Attention!
When the input capture module is enabled, a user software has to enable that the ICx input pin is configured as the input pin by setting the associated TRIS bit. By enabling the input capture module the pin ICx is not configured automatically. Also, all other peripherals using this pin have to be disabled.

Fig. 5-3a Pin diagram of dsPIC30F4013

Fig. 5-3b Pin diagram of dsPIC30F6014A

Finally, a description of the registers of the input capture module of microcontroller dsPIC30F4013 is presented.

Table 5-1 Input capture module registers

ICSIDL – Input captur module stop in IDLE control bit 
        (ICSIDL=0 input capture module will continue to operate in IDLE mode, 
        ICSIDL=1 input capture module will halt in IDLE mode)
        
ICTMR – Input capture timer select bits (ICTMR=0 TMR3 contents are captured on capture event, 
        ICTMR=1 TMR2 contents are captured on capture event)

ICI <1:0> - Select number of captures per interrupt bits
      00 – interrupt on every capture event
      01 – interrupt on every second capture event
      10 – interrupt on every third capture event
      11 – interrupt on every fourth capture event
    
ICOV – FIFO buffer overflow status flag (read only) bit

ICBNE – FIFO buffer buffer empty status (read only) bit 
        (ICBNE=0 FIFO buffer empty, ICBNE=1 FIFO buffer contains at least one capture value
  
ICM <2:0> - Input capture mode select bits
      000 – Input capture module turned off
      001 – Capture mode, every edge (rising or falling)
      010 – Capture mode, every falling edge
      011 – Capture mode, every rising edge
      100 – Capture mode, every 4th rising edge
      101 – Capture mode, every 16th rising edge  
      110 – Unused (module disabled)
      111 – Input capture module in external signal interrupt mode 
      (external source of interrupt requests)

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