Programming dsPIC MCU in PASCAL

Chapter3: Interrupts and Traps

3.1 Interrupts

Interrupts are unexpected events in a sequence of execution of instructions causing an interruption of the normal programme flow. The causes of interrupts can be different. For the family of dsPIC30F microcotrollers, in the transducer or general purpose applications, 41 interrupt sources and 4 types of traps, ranked according to the priority schematic, have been specified.

For each specified interrupt or trap the microcontroller (MCU) has a clearly defined further programme sequence specified by the interrupt vector table (IVT). The IVT contains the initial addresses of interrupt routines for each interrupt source or trap. IVT is located in the programme memory starting at location 0x000004 up to location 0x00007E.

In addition to the interrupt vestor table, in the family of dsPIC30F microcontrollers, the alterante interrupt vector table (AIVT) is also specified. The purpose of the AIVT is to enable the realization of alternate interrupt routines. The AIVT is also located in the programme memory starting at location 0x000084 up to location 0x0000FE.

On the basis of the priorities specified by the special function registers, the interrupt controller is responsible for the preparation and preprocessing of interrupts:

• IFS0<15:0>, IFS1<15:0>, and IFS2<15:0> are the registers containing all the interrupt request flags. Each source of interrupt has a status bit set by the respective peripherals or external signals. These flags are cleared by the user software.
• IEC0<15:0>, IEC1<15:0>, and IEC2<15:0> are the registers containing all the interrupt enable control bits. These control bits are used to individually enable interrupts from the peripherals or external signals.
• IPC0<15:0>, IPC1<15:0>, ... IPC10<7:0> are the registers used to set the interrupt priority level for each of the 41 sources of interrupt.
• IPL<3:0> are the bits containing the current CPU priority level. IPL<3> bit is located in the register CORCON and the remaining three bits IPL<2:0> are in the STATUS register (SR) of the microcontroller.
• INTCON1<15:0> and INTCON2<15:0> are the registers containing global interrupt control functions. INTCON1 contains the control and status bits for the processor trap sources; INTCON2 controls the external interrupt requests behaviour and the use of the alternate vector table by setting the ALTIVT bit (INTCON2<15:0>).

During processor initialization it is necessary to enable interrupts which will be used and assign the corresponding priority levels.

NOTE: Interrupt request flags are set in the IFSx registers irrespective of the interrupt enable bits in the IECx registers. When the conditions for an interrupt to occur are met, the corresponding bits in the IFS are set. Before an interrupt is allowed, the user software has to clear the corresponding IFSx bits because the interrupt controller, upon detecting an interrupt request will not be able to process new interrupt involving these IFSx bits.

Interrupt nesting is enabled by the NSTDIS bit of the control register INTCON1. Nesting of interrupt routines may be optionally disabled by setting this bit. This may be significant if it is necessary to carry out a part of the programme without an interrupt that could change the state which is the basis for this part of the programme or if the interrupt routine changes some variable which are of significance for further execution of the programme.

The priority level of each interrupt is assigned by setting the interrupt priority bits IP<2:0> for each source of interrupt. The bits IP<2:0> are the least significant 3 bits of each nibble (4 bits) within the IPCx register. Bit no. 3 of each nibble iz always zero. The user can assign 7 priority leveles, from 1to 7. Level 7 is the highest and level 1 the lowest priority level for the maskable interrupts, i.e. for the interrupts that could be enabled by the control bits of IECx.

Attention!
If an interrupt is assigned priority level 0, it is the same as if no interrupt is allowed by the bits set in IECx.

Natural order priority is specified by the position of an interrupt in the vector table (IVT). It is used only to resolve conflicts between simultaneous pending interrupts with the same user assigned priority level. Then, the interrupt of the higher natural level of priority is executed first. As an example, table 3-1 shows for the microcontroller dsPIC30F4013 the interrupt vector table (IVT) with all sources of interrupts, interrupt number in the vector table, and the number which defines the natural order priority.

Table 3-1. Interrupt vector table of microcontroller dsPIC30F4013

Example:

The example shows how dsPIC reacts to a rising signal edge at the pin RF6(INT0). For each rising edge the value at port D is incremented by 1.

NOTE: Pins that can be used for external interrupts are model dependent. This example is made for dsPIC30F6014A

program ExtInt1;
procedure IntDetection; org $0014; //Interrupt on INT0
begin
  INC(LATD);
  IFS0.0:=0;        //interrupt flag cleared
end;
begin
  TRISD:=0;     //portd is output
  TRISF:=$FFFF; //portf is input
  IFS0:=0;      //interrupt flag cleared
  IEC0:=1;      //Interrupt is set on a rising edge at INT0 (RF6)
  WHILE TRUE do nop;
end.

Let us summarize the algorithm how dsPIC processes interrupts in this example. Two ports are used, PORTD as the output to display the number of interrupt events and PORTF as the input; this means that an interrupt will occur when at INT0 (RF6) logic 0 changes to logic 1. In the register IEC0 the least significant bit (IEC0.0) is set for allowing reaction to interrupt INT0. The meanings of other bits are shown in table 3-7. When an interrupt occurs, the procedure IntDetection is called. How does dsPIC “know” to call exactly this procedure? By instruction org in the interrupt vector table (see table 3-1) at the memory location 0x000014 is written the procedure IntDetection.

What does dsPIC do when an interrupt occurs, i.e. when at RF6 logic 1 appears after logic 0? At first, it writes logic 1 in the least significant bit of the register IFS0. Then, it tests if the interrupt INT0 is enabled (the least significant bit of IEC0). If yes, it reads from the interrupt vector table which part of the programme should be executed. MicroPascal compiler will, at position 0x000014, write the code where procedure IntDetection starts and dsPIC will execute this procedure and return to the main program.

Two operations are carried out in the interrupt procedure. At first, the interrupt flag is cleared (dsPIC does not do that automatically, but leaves this to the user software). Then, the value at port D is incremented by 1 with INC(LATD).

What would happen if the interrupt flag in the IFS register was not cleared? If this line is omitted, dsPIC will wait until first interrupt, call and execute the procedure IntDetection. What is the difference? The register IFS0 will still indicate that an interrupt occured. As soon as the microcontroller returns to the main programme and executes one instruction, it would understand that an interrupt occured again and the IntDetection procedure would be called again. This means that IntDetection procedure would be executed after each instruction of the main programme. The reader is encouraged to erase the line IFS0.0:=0; and see what happens.

What is the purpose of WHILE TRUE DO NOP;? When dsPIC comes to the end of a programme, it starts from the beginning as if reset. However, at the end of the programme the compiler inserts an endless loop to prevent this of happening. This has been inserted here to make the reader aware of the existence of this loop and that reseting dsPIC is not possible.

3.2 Traps

Traps can be considered as interrupts that could not be masked by setting interrupt control bits in the interapt enable register IECx. Traps are intended to provide the user a means to correct erroneous operation during debug and development of applications.

NOTE: If the user does not intend to use corrective action in the event of a trap error condition, the interrupt vector table is loaded with the address of a default interrupt routine containing only RESET instruction. If the interrupt vector table is loaded with an erroneous address or the address that does not mean any routine, the erroneous address trap will be generated which may lead to RESET.

The trap conditions can only be detected when the trap occurs. The routing generated by the trap should be able to remove the error that lead to it. Each trap source has a fixed priority, ranging from level 8 to level 15. This means that the IPL3 bit is always set during processing of any trap.

The sources of traps are classified in for groups with the interrupt priority growing.

A. Arithmetic error traps are generated if during arithmetic operations the following errors occur:

1. Divide-by-zero is attempted; the operation will be stopped and the divide by zero trap will be generated (interrupt priority level 8),
2. If the arithmetic error trap is enabled, and if in the course of a mathematical operation the overflow of accumulator A or B occurs (carry-out from bit 31) and the protection bits in the accumulators (31-bit saturation mode) are not enabled (interrupt priority level 9),
3. If the arithmetic error trap is enabled, and if in the course of a mathematical operation a catastrophic overflow of the accumulator A or B occurs (carry-out from bit 39); the accumulator saturation is prevented (interrupt priority level 10),
4. If druring shift operation the shift value exceeds 16 bits when processing words, or 8 bits when processing bytes (interrupt priority level 11).

B. Address error traps are generated if the following operating situations occur (interrupt priority level 13):

1. A misaligned data word (2 bytes) fetch is attempted (word access with an odd effective address),
2. A data fetch from unimplemented data address space of the microcontroller is attempted,
3. An attempt by the programme to address an unimplemented programme memory location of the microcontroller,
4. Access to an instruction within the vector space is attempted,
5. A branch or jump instruction specifies an address from unimplemented address space of the micronotroller,
6. Upon modification of the programme counter (PC) register, a nonexistent programme memory location, unimplemented in the microcontroller, is addressed.

C. Stack error trap is generated if the following events occur (interrupt priority level 13):

1. The stack pointer (SP) value exceeds the value of the SPLIM (Stack Pointer LIMit – set by the user) register, i.e. the stack is exceeded from the upper side,
2. The stack pointer value is below 0x0800, i.e. the stack is exceeded from the lower side.

D. Oscillator failure trap is generated if the external oscillator fails; the reliability of operation of the microcontroller is then based on the internal RC oscillator (interrupt priority level 14).

The traps can be classified in two groups: software and hardware traps. The group of software traps contains traps of priorities from 8 to 11 which arise as a consequence of arithmetic operations. The interrupt routines caused by the software traps are nestable. The group of hardware traps contains traps of priorities from 12 to 15. The interrupt routines caused by the hardware traps are not nestable. The highest priority trap is generated when two hardware traps are in conflict.

The organization of the interrupt vector table and alternate vector table in the programme memory of the family of dsPIC30F microcontrollers is shown in Fig. 3-1.

Fig. 3-1 Organization of the interrupt vector table and alternate interrupt vector table in the program memory of the microcontroller family dsPIC30

For handling interrupts it is necessary to know the interrupt sequence. The interrupt sequence begins by writing an interrupt request, from peripherals or external signals, in the interrupt request bit of the IFSx registers at the beginning of each instruction cycle. An interrupt request (IRQ) is identified through setting the corresponding bit in the IFSx register. The interrupt is generated only if it is enabled, i.e. if the corresponding bit in the IECx register is set. In the course of executing the current instruction cycle the priority levels of all pending interrupts are evaluated. If the priority level of a pending interrupt is higher than the priority level currenty processed by the microcontroller (defined by the bits IPL<3:0>), an interrupt is generated.

Upon generating an interrupt, the microcontroller saves on the software stack the current PC value and the low byte of the processor status register (SRL). The byte SRL contains the priority level of the interrupt being processed until then. After that the microcontroller sets the new interrupt priority level in the STATUS register, equal to the level of the generated interrupt. In this way generating any interrupts of a lower level is prevented. The microcontroller does not automatically take care of the rest of the processor context. This task is undertaken by the compiler who saves PC, SRL, and the values of other registers significant for further execution of the programme.

The instruction RETFIE (RETurn From IntErrupt) denotes return from interrupt and unstacks the PC return address and the low byte of the processor status register in order to return the microcontroller to the state and priority level existing prior to the interrupt sequence.

Attention!
The user could lower the priority level of the interrupt being processed by writing a new value in the STATUS register (SR) while processing the interrupt, but the interrupt routine has to clear the interrupt request bit in the IFSx register in order to prevent a recurrent generation of interrupts. The recurrent generation of interrupts could easily lead to stack overflow and the generation of a stack error trap and the microcontroller reset.

NOTE: While processing interrupts the bit IPL3 is always zero. It is set only while processing the processor traps.

For handling interrups in practice, it is necessary to know that the family of microcontrollers dsPIC30F supports up to 5 external interrupt sources, INT0 – INT4. These inputs are edge sensitive, i.e they require transition from low to high logic level or vice versa in order to generate an interrupt. The INTCON2 register contains bits INT0EP – INT4EP defining the polarity of the sensitive edge, i.e. rising or falling edge of the signal.

Very often interrupts are used for waking-up the microcontroller from SLEEP or IDLE mode if the microcontroller is in these states when an interrupt is generated. The SLEEP or IDLE states are used when the minimization of the power consumption or minimization of the noise in the course of AD converter measurement are required. The microcontroller will wake-up and initiate the execution of interrupt routine only if the interrupt request is enabled in the IECx register.

The following example shows how a trap operates in practice

Example:

A programme contains a mistake. There is a chance of divide by zero. Since this is not correct, it is possible that this mistake, if there was not the procedure ment to react, wouls reset dsPIC. This example uses the code from the example of interrupts. On each increasing edge of the bit RF6 the value at port B is decremented by 1 and thus approaches zero which is undesirable because of the danger of dividing by the value of port B in the main programme. The programme is as follows:

program Traps1;
var
  a:word;
procedure IntDet; org $0014;    //vector INT0
begin
  Dec(LATB);    //portB is decremented
  IFS0.0:=0;    //interrupt flag cleared
end;

procedure TrapTrap; org $000C;
begin
  INTCON1.4:=0;
  {the problem is solved by setting
   port B to a nonzero value}
  LATB:=3;
  Inc(LATD);
end;

begin
  TRISB:=0;
  TRISD:=0;
  TRISF:=$FFFF;
  LATB:=3;
  LATD:=0;
  IFS0:=0;     //interrupt flag cleared
  INTCON1:=0;  //trap flag cleared
  IEC0:=1;     //interrupt on rising edge INT0 (RF6) enabled
  while true do
    begin
     a:=256 div LATB;    //if LATB=0 error occured and TrapTrap is called
    end;
end.

A description of the interrupt registers of the microcontroller dsPIC30F4013 is presented at the end of this chapter.

NOTE: Reading bits with no function assigned gives ‘0’.

Table 3-2. Interrupt control register - INTCON1

Table 3-2. continued

NSTDIS – Interrupt nesting disable bit
OVATEN – Accumulator A overflow trap enable bit
OVBTEN – Accumulator B overflow trap enable bit
COVTE – Catastrophic overflow trap enable bit
MATHERR – Arithmetic error trap status bit
ADDRERR – Address error trap status bit
STKERR – Stack error trap status bit
OSCFAIL – Oscillator failure trap status bit

Table 3-3. Interrupt control register 2 - INTCON2

Table 3-3. continued

ALTIVIT – Enable alternate interrupt vector table bit
INT0EP, INT1EP, INT2EP – External interrupt edge detect polarity bits

Table 3-4. Interrupt flag status register - IFS0

Table 3-4. continued

CNIF – Input change notification flag status bit
MI2CIF – I2C module (master mode) transmitter interrupt flag status bit
SI2CIF – I2C module (slave mode) receiver interrupt flag status bit
NVMIF – Non-volatile memory write complete interrupt flag status bit
ADIF – A/D conversion complete interrupt flag status bit
U1TXIF – UART1 transmitter interrupt flag status bit
U1RXIF – UART1 receiver interrupt flag status bit
SPI1IF – SPI1 interrupt flag status bit
T3IF – Timer 3 interrupt flag status bit
T2IF - Timer 2 interrupt flag status bit
OC2IF – Output compare channel 2 interrupt flag status bit
IC2IF – Input capture channel 2 interrupt flag status bit
T1IF – Timer1 interrupt flag status bit
OC1IF – Output compare channel 1 interrupt flag status bit
IC1IF – Input captue channel 1 interrupt flag status bit
INT0IF – External interrupt 0 flag status bit

Table 3-5. Interrupt flag status register - IFS1

Table 3-5. continued

C1IF – CAN1 (combined) interrupt flag status bit
U2TXIF – UART2 transmitter interrupt status bit
U2RXIF – UART2 receiver interrupt flag status bit
INT2IF – External interrupt 2 flag status bit
T5IF – Timer5 interrupt flag status bit
T4IF – Timer4 interrupt flag status bit
OC4IF – Output compare channel 4 interrupt flag status bit
OC3IF- Output compare channel 3 interrupt flag status bit
IC8IF – Input capture channel 8 interrupt flag status bit
IC7IF - Input capture channel 7 interrupt flag status bit
INT1IF – External interrupt 1 flag status bit

Table 3-6. Interrupt flag status register 2 - IFS2

Table 3-6. continued

LVDIF – Programmable low voltage detect interrupt flag status bit
DCIIF – Data converter interface interrupt flag status bit

Table 3-7. Interrupt enable control register 0 - IEC0

Table 3-7. continued

CNIE – Input change notification interrupt enable bit
MI2CIE – I2C module (master mode) transmitter interrupt enable bit
SI2CIE – I2C I2C module (slave mode) receiver interrupt enable bit
NVMIE – Non-volatile memory write complete interrupt enable bit
ADIF – A/D conversion complete interrupt enable bit
U1TXIE – UART 1 transmitter interrupt enable bit
U1RXIE – UART 1 receiver interrupt enable bit
SPI1IE – SPI1 interrupt enable bit
T3IE – Timer3 interrupt enable bit
T2IE – Timer2 interrupt enable bit
OC2IE – Output compare channel 2 interrupt enable bit
IC2IE – Input capture channel 2 interrupt enable bit
T1IE – Timer1 interrupt enable bit
OC1IE – Output compare channel 1 interrupt enable bit
IC1IE – Input capture channel 1 interrupt enable bit
INT0IE – External interrupt 0 enable bit

Table 3-8. Interrupt enable control register 1 - IEC1

Table 3-8. continued

C1IE – CAN1 (combined) interrupt enable bit
U2TXIE – UART2 transmitter interrupt enable bit
U2RXIE – UART2 receiver interrupt enable bit
INT2IE – External interrupt 2 enable bit
T5IE – Timer5 interrupt enable bit
T4IE – Timer4 interrupt enable bit
OC4IE – Output compare channel 4 interrupt enable bit
OC3IE – Output compare channel 3 interrupt enable bit
IC8IE – Input capture channel 8 interrupt enable bit
IC7IE – Input capture channel 7 interrupt enable bit
INT1IE – External interrupt 1 enable bit

Table 3-9. Interrupt enable control register 2 - IEC2

Table 3-9. continued

LVDIE – Programmable low voltage detect interrupt enable bit
DCIIE – Data converter  interface interrupt enable bit

Table 3-10. Special function registers associated wuth interrupt controllers

Table 3-10. continued

T1IP<2:0> - Timer1 interrupt priority bits
OC1IP<2:0> - Output compare channel 1 interrupt priority bits
IC1IP<2:0> – Input capture channel 1 interrupt priority bits
INT0IP<2:0> - External interrupt 0 priority bits
T3IP<2:0> - Timer3 interrupt priority bits
T2IP<2:0> - Timer2 interrupt priority bits
OC2IP<2:0> - Output compare channel 2 interrupt priority bits
IC2IP<2:0> -Input capture channel 2 interrupt priority bits
ADIP<2:0> - A/D conversion complete interrupt priority bits
U1TXIP<2:0> - UART1 transmitter interrupt priority bits
U1RXIP<2:0> - UART1 receiver interrupt priority bits
SPI1IP<2:0> - SPI1 interrupt priority bits
CNIIP<2:0> - Input change notification interrupt priority bits
MI2CIP<2:0> - I2C module (master mode) transmitter interrupt priority level bits
SI2CIP<2:0> - I2C module (slave mode) receiver interrupt priority level bits
NVMIP<2:0> - Non-volatile memory write interrupt priority bits
OC3IP<2:0> - Output compare channel 3 interrupt priority bits
IC8IP<2:0> - Input compsre channel 8 interrupt priority bits
IC7IP<2:0> - Input compare channel 7 interrupt priority bits
INT1IP<2:0> - External interrupt 1 priority bits
INT2IP<2:0> - External interrupt 2 priority bits
T5IP<2:0> - Timer5 interrupt priority bits
T4IP<2:0> - Timer4 interrupt priority bits
OC4IP<2:0> - Output compare channel 4 interrupt priority bits
C1IP<2:0> - CAN1 (combined)interrupt priority bits
SPI2IP<2:0> - SPI2 interrupt priority bits
U2TXIP<2:0> - UART2 transmitter interrupt priority bits
U2RXIP<2:0> - UART2 receiver interrupt priority bits
LVDIP<2:0> - Programmable low voltage detect interrupt priority bits
DCIIP<2:0> - Data converter interface interrupt priority bits

← previous chapter | table of contents | next chapter →