Chapter2: Configuration Bits
Introduction
Prior to the start of programming a microcontroller, it is necessary to set the conditions governing the operation of the microcontroller. The governing conditions imply the clock defining the speed of execution of instructions, the source of the clock, the protection against instabilities of the power supply, the protection against irregular execution of the parts of the program (through WATCHDOG timer, to be descibed later), etc.
The configuration of a microcontroller is carried out by the four registers:
| Register | Name | Address |
| FOSC | Oscillator Configuration Register | 0xF80000 |
| FWDT | Watchdog Timer Configuration Register | 0xF80002 |
| FBORPOR | BOR and POR (Voltage Protection) Configuration Register | 0xF80004 |
| FGS | General Code Segment Configuration Register | 0xF8000A |
These registers are in the programming memory in the upper half of the memory. Details concerning the programming memory can be found in Chapter 8 of the book. It is important to know that the locations in the programming memory are 24-bit wide.
Attention!
The access to the configuration registers is enabled only during configuration of the microcontroller. Any attempt to access the configuration registers in terms of the programming code will result in the microcontroller reset.
2.1 Oscillator configuration register (FOSC)
The oscillator configuration register is used for adjusting the clock of the microcontroller. The clock is of direct influence on the speed of execution of instructions. It is thus essential that the clock is selected correctly. It is also essential to select the oscillator source. The source can be the internal RC oscillator (FRC – internal fast RC oscillator, LPRC – internal low power RC oscillator) or external oscillator (ERC – external RC oscillator, XT – external quartz).
The internal RC oscillator is insufficiently accurate for the majority of microcontroller applications. It is its dependence on the supply voltage and temperature that makes it unacceptable. Besides the internal RC oscillator, it is possible to use an external crystal resonator as a source of the clock. Its frequency could vary from 200kHz to 25MHz. The trird option is to use an external clock (external oscillator or the clock from another instrument). If an external source of the clock or a crystal resonator is used, it is possible to use the internal PLL and increase the internal clock (the clock of the execution of instructions) by factor 4, 8, or 16.
The internal clock, of period TCY, controlling the execution of instructions, is obtained when the clock (from the PLL or directly) is divided by 4. Let a 10MHz crystal resonator and PLL 4x are selected. This means that the internal clock is 4x10MHz =40MHz. This value is divied by 4 to obtain 10MHz (100ns period). This implies that one instruction is executed in 100ns, the internal clock period. In the majority of processes it is very important to know the times of the execution of parts of the program. For these calculations it is necessary to know the internal clock period of the microcontroller.
The oscillator configuration register: selects the source of the clock, controls the activation and mode of thePLL, enables the permission to switch to another source of the clock during operation, and controls monitoring of the clock.
The family of dsPIC30F microcontrollers has the ability that during operation, if it becomes necessary (e.g. one source of the clock fails), can switch to another source of the clock. This ability provides a whole spectrum of applications of the dsPIC30F family of microcontrollers. It is possible to provide an additional stability of the clock, switch to a faster source of the clock within the parts of the program that have to be executed faster, swith to the low power operation, etc. The structure of the oscillator configuration register is given in Table 2-1.
| name | ADR | 23-16 | 15-14 | 13 | 12 | 11 | 10 | 9-8 | 7 | 6 | 5 | 4 | 3-0 |
| FOSC | 0xF80000 | - | FCKSM<1:0> | - | - | - | - | FOS<1:0> | - | - | - | - | FPR<3:0> |
Table 2-1 Description of the oscillator configuration register FOSC
FCKSM <1:0> - Clock switching selection
Clock monitoring selection
1x - Switching between different sources of the clock is disabled.
Clock monitoring is disabled.
01 - Switching between different sources of the clock is enabled.
Clock monitoring is disabled.
00 - Switching between different sources of the clock is enabled.
Clock monitoring is enabled.
FOS <1:0> - Definition of the clock source.
11 - Primary oscillator selected by FPR<3:0>
10 -Internal low power RC oscillator
01 -Internal fast RC oscillator
00 - Low power 32kHz internal oscillator (timer 1)
FPR <3:0> - Selection of the mode of generating the internal clock
1111 - EC PLL 16x - External clock mode with 16x PLL enabled.
External clock at OSC1, OSC2 pin is I/O
1110 – EC PLL 8x - External clock mode with 8x PLL enabled.
External clock at OSC1, OSC2 pin is I/O
1101 – EC PLL 4x - External clock mode with 4x PLL enabled.
External clock at OSC1, OSC2 pin is I/O
1100 – ECIO – External clock mode without PLL.
External clock at OSC1, OSC2 pin I/O
1011 – EC – External clock mode. OSC2 pin is system clock output (Fosc/4)
1010 – Reserved
1001 – ERC – External RC oscillator mode. OSC2 pin is system clock output (Fosc/4)
1000 – ERCIO – External RC oscillator mode. OSC2 pin is I/O
0111 – XT PLL 16x – XT crystal oscillator mode with 16xPLL enabled. 4 – 10MHz crystal
0110 – XT PLL 8x – XT crystal oscillator mode with 8xPLL enabled. 4 – 10MHz crystal
0101 – XT PLL 4x - XT crystal oscillator mode with 46xPLL enabled. 4 – 10MHz crystal
0100 – XT - XT crystal oscillator mode (4 – 10MHz crystal)
001x - HS - HS crystal oscillator mode (10 – 25MHz crystal)
000x – XTL - XTL crystal oscillator mode (200kHz – 4MHz crystal)
2.2 Configuration register of the watchdog timer (FWDT)
The configuration register of the watchdog timer serves for swithing on and off of the watchdog timer and for the adjustment (preseting) of its operation. The preset value is a number dividing the internal RC clock to obtain, in this case, the clock of the watchdog timer. The watchdog timer is independent of the internal clock which governs the execution of instructions. In this way an operative timer is obtained even if the internal clock fails. The frequency of the RC oscillator for the watchdog timer is 512kHz. After the initial division by 4 one obtains the 128kHz which is the basic clock of the watchdog timer.
The basic clock 128kHz of the watchdog timer is divided by two progammable values. The first is prescaler A and the second prescaler B. After division, the internal clock of the watchdog timer is obtained. With this clock an 8-bit register is incremented. When the value in the register reaches the maximum of 255, the watchdog timer resets the microcontroller or switches the microcontroller from inactive to active state. If the microcontroller is in the inactive (SLEEP) state, the watchdog swithes it into the active state and the execution of the current program continues. If the microcontroller is in the active mode, i.e. the execution of the current program is on, the watchdog timer will, upon the expiration of the defined time, reset the micricontroller.
The time interval when the wacthdog sends the reset/wake-up signal is calculated as follows. The period of the basic clock is 1/(128 kHz) = 7.8125µs. This value is multiplied by the prescaler A and prescaler B values. This gives the clock period of the watchdog timer. This period multiplied by 255 gives the maximum value the register will be incremented. This value is the time the watchdog timer will wait before it generates the reset/wake-up signal of the microcontroller. The waiting times, in milliseconds, depending on the values of prescaler A and prescaler B, are given in table 2-2.
| Prescaler B value | Prescaler A value | |||
| 1 | 8 | 64 | 512 | |
| 1 | 2 | 16 | 128 | 1024 |
| 2 | 4 | 32 | 256 | 2048 |
| 3 | 6 | 48 | 384 | 3072 |
| 4 | 8 | 64 | 412 | 4096 |
| 5 | 10 | 80 | 640 | 5120 |
| 6 | 12 | 96 | 768 | 6144 |
| 7 | 14 | 112 | 896 | 7168 |
| 8 | 16 | 128 | 1024 | 8192 |
| 9 | 18 | 144 | 1152 | 9216 |
| 10 | 20 | 160 | 1280 | 10240 |
| 11 | 22 | 176 | 1408 | 11264 |
| 12 | 24 | 192 | 1536 | 12288 |
| 13 | 26 | 208 | 1664 | 13312 |
| 14 | 28 | 224 | 1792 | 14336 |
| 15 | 30 | 240 | 1920 | 15360 |
| 16 | 32 | 256 | 2048 | 16384 |
Table 2-2 Waiting times of the watchdog timer
Example:
Let the execution of a part of the program, depending on an external signal, should not last longer than 100ms. In this case the watchdog timer can be activated with the period of 100ms. If it occus that the signal is 100ms late, the microcontroller is reset and the execution of the program starts from the beginning. The watchdog timer should be configured to perform a given function. It is impossible to achieve the waitng time of 100ms, so the period of 112ms (see table 2-2) will be used as the shortest waiting time after 100ms. This is accomplshed with the values of prescaler A = 8 and prerscaler B = 7.
If the program is to function correctly, it is necessary to reset at times the value in the watchdog register. This is achieved by the assembler instruction CLRWDT.
The watchdog timer is configured by the FWDT register. The structure of the configuration register of the watchdog timer is shown in table 2-3.
| name | ADR | 23-16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5-4 | 3-0 |
| FWDT | 0xF0002 | - | FWDTEN | - | - | - | - | - | - | - | - | - | FWPSA<1:0> | FPR<3:0> |
Table 2-3 The configuration register od the watchdog timer FWDT
FWDTEN – Watchdog enable configuration bit
1 – Watchdog enabled; LPRC osillator can not be disabled
0 – Watchdog disabled
FWPSA <1:0> - Selected value of prescaler A
11 = 1:512
10 = 1:64
01 = 1:8
00 = 1:1
FWPSB <1:0> - Selected value of prescaler B
1111 = 1:16
1110 = 1:15
....
....
....
0001 = 1:2
0000 = 1:1
Fig. 2-1 The algorithm of the watchdog timer
2.3 Voltage protection configuration register (FBORPOR)
The configuration register of the voltage protection serves for defining the minimum value of the supply voltage, switching on/off the circuit for reseting the microcontroller if the supply voltage falls bellow the specified value, and for adjustment of the PWM output.
The proper execution of programs requires a godd stability of the power supply. The family of microcontrollers dsPIC30F has the ability of defining a minimum power supply voltage ensuring proper functioning of the device. If the supply voltage falls below this limit, the internal circuit will reset the microcontroller, wait until the supply voltage returns above the limit, and after the specified power-up delay time activate the microcontroller starting the execution of the program for the beginning.
The adjustment of the PWM output, more elaborated in Chapter 6 Output Compare Module, makes also the contents of this register. It is possible to select the states of PWM pins at a device reset (high impedance or output) and the active signal polarity for the PWM pins. The polarity for the high side and low side PWM pins may be selected independently.
| name | ADR | 23-16 | 15 | 14-11 | 10 | 9 |
| FBORPOR | 0x80004 | - | MCLREN | - | PWMPIN | HPOL |
Table 2-4. The voltage protection configuration register FBORPOR
| 8 | 7 | 6 | 5-4 | 3-2 | 1-0 |
| LPOL | BOREN | - | BORV<1:0> | - | FPWRT<1:0> |
(Table 2-4. continued)
MCLREN – Pin function enable bit
below the specified value
1 - Pin function enabled (default)
0 - Pin is disabled
PWMPIN – The state of PWM at device reset
1 - PWM pin is in the state of high impedance at device reset
0 - PWM pin is configured as output at device reset
HPOL – High side polarity bit
1 - High side output pin has active-high output polarity
0 - High side output pin has active-low output polarity
LPOL - Low side polarity bit
1 - Low side output pin has active-high output polarity
0 - Low side output pin has active-low output polarity
BOEN – Enable bit
1 - PBOR enabled
0 - PBOR disabled
BORV <1:0> - Minimum supply voltage select bits
11 - 2.0V
10 - 2.7V
01 - 4.2V
00 - 4.5V
FPWRT <1:0> - Power-on reset timer value selection bits
11 - 64ms
10 - 16ms
01 - 4ms
00 - 0ms
2.4 Program memory protection configuration register (FGS)
The program memory protection configuration register is used to code protect or write protect the program memory space. It includes all user program memory with the exception of the interrupt vector table space.
If the program memory is code protected, the device program memory can not be read from the device using in-circuit serial programming or the device programr. Further code cannot be programd into the device without first erasing the entire general code segment.
The program memory protection register uses only two configuration bits, the others are unimplemented. The two configuration bits must be programd as a group, i.e. it is not possible to change only one of them.
If the code protect and write protect of the program memory are enabled, a full chip erase must be performed to change the state of either bit.
The structure of the program memory protection configuration register is shown in table 2-5.
| name | ADR | 23-16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FGS | 0x8000A | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
Table 2-5. Program memory protection configuration register FGS
GCP - Program memory code protect enable
1 - Program memory is not code protected
0 - Program memory is code protected
GWRP - Program memory write protect enable
1 – Program memory is not write protected
0 - Program memory is write protected