The Universal Asynchronous Receiver Transmitter (UART) module is the basic serial I/O module available in the dsPIC30F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, RS-232, and RS-485 interfaces.
The primary features of the UART module are:
Each dsPIC30F device variant may have one or more UART modules (e.g. dsPIC30F4013 has 2 UART modules).
Fig. 10-1 shows a simplified block diagram of the UART module. The UART module consists of the three key hardware elements: Baud-rate generator, asynchronous transmitter, and asynchronous receiver.
Fig. 10-1 UART simplified block diagram
The UART module includes a dedicated 16-bit baud rate generator with a prescaler. The UxBRG register controls the period of a free-running 16-bit timer:
the value of the UxBRG register for a specified baud rate is given by
If FCY=8MHz, and the desired baud rate is 9600, by applying the above expression one obtains the value UxBRG=(8•106/(16•9600))-1=51.083. After truncation to the integer value UxBRG=51. The truncation introduced a deviation from the desired baud rate. The new baud rate for UxBRG=51 is 9615.384, i.e. the deviation is 0.16%.
The baud rate and the deviation from a desired baud rate are strongly dependent on the basic clock of the device and the instruction cycle FCY. UART baud rates, baud rate deviations, and UxBRG register values as functions of the device instruction cycle frequencies are shown in Table 10-1.
|Baud rate [Kbps]||Fcy=30MHz||Fcy=25MHz||Fcy=20MHz||Fcy=16MHz|
|KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG|
|Baud rate [Kbps]||Fcy=12MHz||Fcy=10MHz||Fcy=8MHz||Fcy=7.68MHz|
|KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG|
|Baud rate [Kbps]||Fcy=5MHz||Fcy=4MHz||Fcy=3.072MHz||Fcy=1.8432MHz|
|KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG||KBAUD||Error [%]||BRG|
Table 10-1 Baud rates, baud rate deviations, and UxBRG register values as functions of the device instruction cycle frequencies
The minimum baud rate is FCY/(16•65535) for UxBRG=0xFFFF. The maximum baud rate is FCY/16 for UxBRG=0. Writing a new value to the UxBRG register causes the BRG timer to be cleared. This ensures that the BRG immediately starts generating the new baud rate.
The UART uses standard non-return-to-zero (NRZ) format consisting of one START bit, eight or nine data bits, and one or two STOP bits. To increase data transmission noise immunity, parity is supported by the hardware. The UART may be configured by the user as even (logic zero or logic one is added to make the total number of units in a message even), odd or no parity.
The most common data format is 8 bits, no parity and one STOP bit (denoted as 8, N, 1), which is the default setting.
The number of data bits and the parity are specified in the PDSEL<1:0> (UxMODE<2:1>) and the number of STOP bits in the STSEL (UxMODE<0>) control bit.
The UART baud rate is configured by setting the UxBRG register.
The UART module transmits and receives the LSb first. The UART's transmitter and receiver are functionally independent, but use the same data format and baud rate.
The UART module is enabled by setting the UARTEN (UxMODE<15>) control bit. The transmit mode of the UART module is enabled by the UTXEN (UxSTA<10>) bit. Once enabled, the UxTX and UxRX pins are configured as an output and an input, respectively, overriding the TRIS and PORT register bit settings for the corresponding I/O port pins. The UxTX is at logic '1' when no transmission is taking place. The UART module is disabled by clearing the UARTEN (UxMODE<15>) control bit. This is the default state after any RESET. If the UART module is disabled, all UART pins operate as port pins under the control of their corresponding PORT and TRIS bits. Disabling the UART module resets the FIFO buffers to empty states and the baud rate counter is reset.
When the UARTEN (UxMODE<15>) bit is cleared, all error and status flags associated with the UART module: URXDA, OERR, FERR, PERR, UTXEN, UTXBRK, and UTXBF are cleared, whereas the RIDLE and TRMT bits are set to '1'. Other control bits are of no influence as long as UARTEN= 0. Clearing the UARTEN bit while the UART is active will abort all pending transmissions and receptions and reset the module. Re-enabling the UART will restart the UART in the same configuration.
Some dsPIC30F devices have an alternative set of UART transmit and receive pins that can be used for serial communication. These are very useful when the primary UART pins are shared by other preipherals. The alternate I/O pins are enabled by setting the ALTIO control bit. If ALTIO=1, the UxATX and UxARX pins are used by the UART module, instead of UxTX and UxRX.
The UART transmitter block diagram is shown in Fig. 10-2. The heart of the transmitter is the transmit shift register UxTSR where parallel data (9-bit word) are converted to serial data sequences. The shift register obtains its data from the transmit FIFO buffer, TxTXREG. The write-only UxTXREG register is loaded with data by the user software. The UxTXREG is not loaded until the STOP bit has been transmitted from the previous load. As soos as the STOP bit is transmitted, the UxTSR is loaded with new data from the UxTXREG register (if available).
Fig. 10-2 UART transmitter functional block diagram
The registers UxTXREG and UxTSR are 9-bit wide, i.e. data write to the transmit FIFO buffer through the register UxTXREG is done in bytes (8-bit). The UxTSR register is not mapped in data memory, thus it is not available to the user.
The UART transmission is enabled by setting the UTXEN enable bit (UxSTA<10>). The actual transmission will not occur until the UxTXREG has been loaded with data and the baud rate generator has produced a shift clock, in accordance with the value in the register UxBRG. The transmission can also be started by first loading the UxTXREG register and the setting the UTXEN enable bit.
Clearing the UTXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the UxTX pin will revert to a high-impedance state.
In order to select 9-bit transmission, the PDSEL<1:0> bits (UxMODE<2:1>) should be set to '11' and the ninth bit should be written to the 9th location of the UxTxREG register (UxTXREG<8>). A word (16-bit) should be written to UxTXREG so that all nine bits are written at the same time.
NOTE: There is no parity in the case of 9-bit data transmission.
The data transmit FIFO buffer consists of four 9-bit wide memory locations. The UxTXREG register provides user access to the next available buffer location. The user may write up to 4 words in the buffer. Once the first location in the transmit FIFO buffer is loaded to the shift register UxTSR, that location becomes available for new data to be written and the next location is sourced to the UxTSR register. The UTXBF status bit is set whenever the buffer is full (all four locations). If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO.
The FIFO is reset during any device RESET, but is not affected when the device enters SLEEP or IDLE mode or wakes up from SLEEP or IDLE mode.
The transmit interrupt flag (UxTXIF) is located in the corresponding interrupt flag status (IFS) register. The UTIXSEL control bit (UxSTA<15>) determines when the UART will generate a transmit interrupt.
- If UTXISEL = 0, an interrupt is generated when a word (8- or 9-bit) is transferred from the transmit FIFO buffer to the transmit shift register (UxTSR). This implies that the transmit buffer has at least one empty word. An iterrupt is generated very often. If the UART module is to operate in this mode, it is required that the corresponding interrupt service routine is very quick, i.e. it should be completed before the transmission of the next word.
- If UTXISEL = 1, an interrupt is generated when a word is transferred from the transmit FIFO buffer to the transmit shift register (UxTSR) and the transmit buffer is empty. Since an interrupt is generated only after all 4 words have been transmitted, this 'block transmit' mode is useful if the interrupt service routine cannot be performed very quickly.
When the UTXEN enable bit is set, an interrupt request will be generated. The interrupt request should be reset by the user software. If UTXISEL = 0, an interrupt request will be generated on setting the UTXEN since there is at least one empty location in the transmit FIFO buffer; if UTXISEL = 1, an interrupt request will be generated on setting the UTXEN since the transmit FIFO buffer is empty.
While the UxTXIF flag bit indicates the status of the UxTXREG register, the TRMT (UxSTA<8>) status bit shows the status of the UxTSR register. The TRMT status bit is a read only bit, which is set when the UxTSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the UxTSR register is empty.
When setting up a transmission, the following steps should be undertaken:
Fig. 10-3 shows the waveforms of an example of serial data transmission (8-bit or 9-bit) by the UART module. Fig. 10-4 shows the waveforms of an example of serial data transmission for a sequence of two bytes.
Fig. 10-3 Waveforms of serial data transmission (8 or 9-bits)
Fig. 10-4 Waveforms of serial data transmission (sequence of two bytes)
For sending a break character (symbol), the UTXBRK (UxSTA<11>) bit must be set by software. Setting this bit forces the output pin UxTX to logic zero. Setting the UTXBRK bit will override any other transmitter activity. The user should wait for the transmitter to complete the current transmission before setting UTXBRK.
To send a break character, the UTXBRK bit must be set by software and remain set for a minimum of 13 baud clocks.The baud clock periods are timed in software. The UTXBRK bit is then cleard by software to generate the STOP bit (one or two, defined by the configuration). The user must wait one or two baud clocks to ensure a valid STOP bit(s) before loading data to the FIFO buffer via the UxTXREG register.
Sending a break character does not generate a transmitter interrupt.
The UART receiver functional block diagram is shown in Fig. 10-5. The heart of the receiver is the receive shift register UxRSR where a serial sequence is converted to a parallel word (9-bit word). After sampling the UxRX pin for the STOP bit, the received data in UxRSR are transferred to the receive FIFO buffer, if it is empty.
Fig. 10-5 UART receiver functional block diagram.
The data on the UxRX pin are sampled three times by a majority detect circuit to determine if a high or a low level is present at the UxRX pin.
The UxRSR register is nor mapped in data memory, so it is not available to the user.
The FIFO receive data buffer consists of four 9-bit wide memory locations. The access to the contents of the receive FIFO buffer is via the UxRXREG read-only register. It is possible for 4 words of data to be received and transferred to the FIFO buffer and a fifth word to begin shifting data to the UxRSR register before a buffer overrun occurs. When the FIFO is full (four characters) and a fifth character is fully received into the UxRSR register, the overrun error bit OERR (UxSTA<1>) will be set. The word in UxRSR will be kept, but further transfers to the receive FIFO are inhibited as long as the OERR bit is set. The user must clear the OERR bit in software to allow further data to be received. Clearing the OERR bit, clears the receive FIFO buffer.
The data in the receive FIFO should be read prior to clearing the OERR bit. The FIFO is reset when OERR is cleared, which causes data in the buffer to be lost.
The parity error bit PERR (UxSTA<3>) is set if a parity error has been detected in the received data (the last word in the receive FIFO buffer), i.e. the total number of ones in the data is incorrect (odd for EVEN parity mode or even for ODD parity mode). The PERR bit is irrelevant in the 9-bit mode. For the 8-bit mode, prior to reading the data from the receive FIFO, the FERR and PERR flags should be checked to ensure that the received data are correct.
The URXISEL<1:0> (UxSTA<7:6>) control bit determines when the UART receiver generates an interrupt. The UART receive interrupt flag (UxRXIF) is located in the corresponding interrupt flag status, IFS register.
Switching between the three interrupt modes during operation of the UART module is possible.
The URXDA bit (UxSTA<0>) indicates whether the receive FIFO buffer is empty. This bit is set as long as there is at least one character to be read from the receive buffer. URXDA is a read only bit.
The URXDA and UxRXIF flag bits indicate the status of the UxRXREG register. The RIDLE bit (UxSTA<4>) shows the state of the shift register UxRSR. The RIDLE status bit is a read only bit, which is set when the receiver is IDLE (i.e. the UxRSR register is empty and there is no current data reception). No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the UxRSR is IDLE.
When setting up a reception, the following steps should be undertaken:
Fig. 10.6 shows an example of serial data reception using the UART transmitter. The waveforms for two 8-bit bytes are shown. Fig. 10-7 shows the reception with a receive overrun of the receive FIFO buffer
Fig. 10-6 Example of serial data reception of two 8-bit bytes
Fig. 10-7 Example of serial data reception with an overrun of the receive FIFO buffer
The UART module is often used for muli-processor communication. In the multi-processor communication typical communication protocols are: data bytes and address/control bytes. A common schematic is to use a 9th data bit to identify whether a data byte is address or data information. If the 9th bit is set, the data is processed as address or control information. If the 9th bit is cleared, the received data word is processed as data associated with the previous address/control byte.
A common multi-processor protocol operates as follows:
The UART receiver can be configured to operate in the address detection mode by setting the ADDEN (UxSTA<5>) control bit. In this mode, the receiver will ignore data words with the 9th bit cleared. This reduces the number of interrupts of the UART module, since data words with the 9th bit cleard are not buffered.
To operate in the address detection mode, the UART must be configured for 9-bit data. The ADDEN bit has no effect when the receiver is configured in 8-bit data mode.
The setup procedure for 9-bit transmission is identical to the 8-bit transmit modes, except that PDSEL<1:9> (UxMODE<2:1>) should be set to '11'.
The setup procedure for 9-bit reception is similar to the 8-bit receive modes, except that PDSEL<1:0> (UxMODE<2:1>) should be set to '11'. The receive interrupt mode should be configured by setting the URXISEL<1:0> (UxSTA<7:6>) control bits.
If the address detect mode is enabled, the URXISEL<1:0> control bits should be configured so that an interrupt will be generated after every received word, i.e. they should be set to '00' or '11'. Each received data word must be checked in software for an address match immediately after reception.
The procedure for using the address detect mode is as follows:
Fig. 10-8 Example of data reception in the address detect mode (ADDEN=1)
The receiver will count and expect a certain number of bit times based on the values programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. If more than 13 bits at the low logic level occur, the BREAK character has been received. After 13 bits at the low logic level, a STOP bit has to be detected. Then, on the basis of the set FERR flag one can conclude that a BREAK character has been transmitted. If the STOP bit has not been received, the RIDLE status bit is at the low logic level, i.e. the receiver had not detected the end of the message,irrespective of the FERR flag.
This example shows the use of the specialized UART library of the mikroBasic compiler for dsPIC devices which greatly facilitates the initiaization of the UART module, writing, and reading data to and from the transmitter and receiver of the UART module, respectively. The example also shows the interconnection of the UART module and the RS-232 transiever and the connection of the UART module to the serial port of a PC.
Fig. 10-9 Connection of the UART module to the serial port of a PC via the RS-232 transiever.
program Uart_Test dim text, delimiter as string dim test as word main: Uart1_Init(9600) 'Initialization of UART module on 9600Kbps delimiter = "stop" 'Delimiter is word "stop" while TRUE if Uart1_Data_Ready() = 1 then 'If data are received Uart1_Read_Text(text, delimiter) 'Only if STOP is received Uart1_Write_Text(text) 'Message is returned (echo) end if wend end.
The program initializes the UART module in the receive and transmit 8-bit format mode, without parity, and with one stop bit. If another format is to be initialized, the procedure Uart1_Init_Advanced instead of Uart1_Init must be used. In this way it is possible to setup 9-bit data or perhaps 8-bit data with an EVEN or ODD parity bit. Also it is possible to select one or two STOP bits. The procedure Uart1_Data_Ready the value of the status bit URXDA (U1STA<0>) is read and the presence of data in the receive FIFO buffer is checked. The procedures Uart1_Write, Uart1_Write_Char, and Uart1_Write_Text data, ASCII character and text are sent respectively via the transmitter of the UART module. Data reception, ASCII character and text is realized by the procedures Uart1_Read, Uart1_Read_Char, and Uart1_Read_Text, respectively. The UART module disable is performed by the procedure Uart1_Disable (clear the UARTEN control bit); the UART module enable is performed by the procedure Uart1_Enable (set the UARTEN control bit).
The UART module has the ability to operate in the loopback mode. This mode allows performing the corresponding self-tests. In order that the UART module operates in the loopback mode, it is required that the LPBACK (UxMODE<6>) control bit is set. In this mode the UxTX output is internally connected to the UxRX input, and the UxRX pin is disconnected from the internal UART receive logic. However, the UxTX pin still functions normally. Sending a message by the UART transmitter causes the reception of this message by the UART receiver. This allows checking if the UART module functions correctly.
To configure the UART module to operate in this mode, the following steps should be taken:
To allow the system to determine baud rates of the received characters, the UxRX input can be internally connected to a selected input capture channel. To operate in this mode, the ABAUD bit (UxMODE<5>) should be set and the UxRX pin is internally connected to the input capture channel. The corresponding ICx pin is disconnected from the input capture channel.
The input capture channel used for auto baud support is device specific. E.g. for dsPIC30F4013 for auto baud support of the UART1 module, the input capture module IC1 is used, whereas for UART2 the input capture module IC2 is used.
This mode is only valid when the UART is enabled (UARTEN=1) and the loopback mode is disabled (LPBACK=0). Also, the user must program the capture module to detect the falling and rising edges of the START bit.
When the device enters IDLE mode, the module can continue normal operation if the USIDL (UxMODE<13>) control bit is cleared. If USIDL=1, the module will stop and any transmission or reception in progress will be aborted.
Fig. 10-10a Pinout of dsPIC30F4013
Fig. 10-10b Pinout of dsPIC30F6014A
At the end, a brief description of the registers of the UART module is presented
|U1BRG||0x0214||Baud-rate generator prescale|
|U2BRG||0x021E||Baud-rate generator prescale|
Table 10-2 Description of UART module registers
Table 10-2 (continued)
UARTEN – UART enable bit (UARTEN=0 UART is disabled, UARTEN=1 UART is enabled) USIDL – Stop in IDLE mode bit (UISDL=0 continue operation in IDLE mode, USIDL=1 discontinue operation in IDLE mode) ALTIO – UART alternate I/O selection bit (ALTIO=0 UART communicates using UxTX and UxRX I/O pins, ALTIO=1 UART communicates using UxATX and UxARX I/O pins) WAKE – Enable wake-up on START bit detect during SLEEP mode bit LPBACK – UART loop back mode select bit ABAUD – Auto baud enable bit PDSEL<1:0> - Parity and data selection bits 00 – 8-bit data, no parity 01 – 8-bit data, even parity 10 – 8-bit data, odd parity 11 – 9-bit data, no parity STSEL – STOP selection bit (STSEL=0 one STOP bit, STSEL=1 two STOP bits) UTXISEL – Transmission interrupt mode selection bit (UTXISEL=0 interrupt when a character is tranferred to the transmit shift register, UTXISEL=1 interrupt when a character is tranferred to the transmit shift register and the transmit buffer becomes empty) UTXBRK – Transmit break bit ( UTXBRK=0 UxTX pin operates normally, UTXBRK=1 UxTX pin is driven low, regardless of transmitter state) UTXEN – Transmit enable bit (UTXEN=0 UART transmitter disabled, UTXEN=1 UART transmitter enabled) UTXBF – Transmit buffer full status bit (UTXBF=0 transmit buffer is not full, UTXBF=1 Transmit buffer is full) TRMT – Transmit shift register is empty bit (TRMT=0 transmit shift register is not empty, transmission in progress, TRMT=1 transmit shift register is empty, transmission completed) URXISEL<1:0> - Receive interrupt mode selection bits 0x – interrupt flag bit is set when a charatcer is received 10 - interrupt flag bit is set when receive buffer is ¾ full (3 locations full) 11 - interrupt flag bit is set when receive buffer is full (all 4 locations full) ADDEN – Address character detect (ADDEN=0 address detect mode disabled, ADDEN=1 address detect mode enabled) RIDLE – Receiver IDLE bit (RIDLE=0 UxRSR not empty, data is being received, RIDLE=1 receiver is IDLE) PERR – Parity error status bit FERR – Framing error status bit OERR – Recive buffer overrun error status bit URXDA – Receive buffer data available bit (URXDA=0 receive buffer is is empty, URXDA=1 receive buffer has data, at least one more character can be read)