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Programming dsPIC MCU in BASIC

Chapter4: Timers

Introduction

Timers are basic peripherals of each microcontroller. Depending upon the model, the dsPIC30F family offers several 16-bit timer modules. Microcontroller dsPIC30F4013 contains 5 timer modules.

Each timer module contains one 16-bit timer/counter consisting of the following registers:

  • TMRx – 16-bit timer counter register,
  • PRx – 16-bit period register containing value of the period,
  • TxCON – 16-bit control register for selecting mode of the timer.

Each timer module also has the associated bits for interrupt control:

  • TxIE – interrupt enable control bit,
  • TxIF – interrupt flag status bit,
  • TxIP<2:0> - three interrupt priority control bits (in the interrupt register IPCx).

Most of the timers in the family of dsPIC30F microcontrollers have the same functional circuitry. Depending of their functional differences, they are classified into three types: A, B, or C. Timers of the types B and C can be combined to form a 32-bit timer.

4.1 Type A timer

Type A timer is available on most dsPIC30F devices. Timer1 is a type A timer. A type A timer has the following unique features over other types:

  • can be operated from the device low power 32 kHz oscillator,
  • can be operated in an asynchronous mode from an external clock source.

The unique feature of a type A timer is that it can be used for real-time clock (RTC) applications. A block diagram of the type A timer is shown in Fig. 4-1.

Type A timer block diagram

Fig. 4-1 Type A timer block diagram

Type A timer is a general purpose (GP) 16-bit timer and in the microcontroller dsPIC30F4013 it is denoted as timer1 module.

Timer1 module is a 16-bit timer primarily intended for use as a real time counter, or universal period meter, or event counter in the free-running mode. Timer1 can be configured to operate as:

  1. a 16-bit timer,
  2. a 16-bit synchronous counter,
  3. a 16-bit asynchronous counter.

Also, timer1 has the ability to operate as a gated timer, select a prescaler, operate during SLEEP or IDLE states of the microcontroller, as well as generate an interrupt request when the value of the register TMR1 equals that of the period register PR1. The condition for generatig an interrupt request could be the falling edge of an external gating signal (TGATE).

Control of the operation of the timer1 module is determined by setting bits in the 16-bit configuration special function register (SFR) T1CON.

4.1.1 16-bit timer mode

In the 16-bit timer mode the value of the TMR1 counter is incremented by each instruction cycle until it is equal to the preset value of the PR1 register, when the counter is reset to ‘0’ and restarted. At this moment an interrupt request for timer1 module T1IF (in the register IFS0) is generated. Processing of this request depends on the interrupt T1IE enable bit (in the IEC0 register). Timer module continues to operate during the interrupt routine.

Timer1 module can operate during the IDLE state if the TSIDL bit (T1CON<13>) is reset, but if this bit is set, the counter continues to operate after the processor is waken-up from IDLE state.

Attention!
Interrupt of timer1 module is generated upon an interrupt request set by timer1 module only if the interrupt is enabled by setting the T1IE bit in the IEC0 register. The interrupt request bit T1IF in the IFS0 register has to be reset by the software after the interrupt is generated.

The following example demonstrates how timer1 module can be used in the 16-bit timer mode.

Example:

Switch on and off a LED diode at port D approximately 4 times per second. This example uses timer1 module having clock 256 times slower then the dsPIC clock. At each 10 000 clocks timer1 module calls interrupt routine Timer1Int and changes the value at port D.

program TestTimer1
sub procedure Timer1Int org $1A ' Timer1 address in the interrupt vector table
  LATD = not PORTD       ' PORTD inversion
  IFS0 = IFS0 and $FFF7  ' Interrupt flag reset
end sub
main:
  TRISD = 0              ' PORTD is output
  LATD  = $AAAA          ' Set initial value at port D
  IPC0  = IPC0 or $1000  ' Priority level is 1
  IEC0  = IEC0 or $0008  ' Timer1 interrupt enabled
  PR1   = 10000          ' Interrupt period is 10000 clocks
  T1CON = $8030          ' Timer1 enabled (internal clock divided by 256)

  while true             ' Endless loop
    nop
  wend
end.

How does one calculate the period of interrupt requests? Let the internal clock be set to 10MHz. The period is 100ns. Since the clock is divided by 256 (prescaler reduces the clock 1:256) to form the timer clock, it follws that the the timer clock is 100*256=25600ns i.e. 25.6µs. At each 10000 clocks an interrupt is requestd, i.e. at each 256ms or approximately 4 times per second.

T = 10000*25.6µs = 256ms ~ ¼s.

4.1.2 16-bit synchronous counter mode

In the 16-bit synchronous counter mode the counter value TMR1 increments on every rising edge of an external clock source. In this mode the phase of the internal clock is synchronized with the external clock. When the value of the TMR1 counter is equal to the preset value of the PR1 register, the counter TMR1 is reset and starts counting from ‘0’. At this moment an interrupt request for timer1 module T1IF (in the register IFS0) is generated. Processing of this request depends on the interrupt T1IE enable bit (in the IEC0 register). Timer module continues to operate during the interrupt routine.

The purpose of the timer1 module is to allow measurement of the periods of very fast clock signals, e.g. autodetection of the speed of communication of the universal serial inteface UART.

The timer1 module could operate in this mode during IDLE state if bit TSIDL (T1CON<13>) is reset; if this bit is set, the counter continues operation after the processor is waken-up from IDLE state.

The following example demonstrates how timer1 module can be used in the synchronous counter mode.

Example:

Count every tenth pulse and increment the value at port D. In this example timer1 is used for counting external clock pulses at pin T1CK. After ten pulses interrupt Timer1Int occurs and the vaule at port D is incremented. Block diagram of Fig. 4-2 shows the interconnection between the timer1 and external clock source.

Block diagram of the connection of an external clock source to dsPIC30F4013

Fig. 4-2 Block diagram of the connection of an external clock source to dsPIC30F4013

program TestTimer1
sub procedure Timer1Int org $1A ' Timer1 address in the interrupt vector table
  LATD = not PORTD       ' Value at PORTD is incermented
  IFS0 = IFS0 and $FFF7  ' Interrupt request is reset
end sub
main:
  TRISD = 0             ' PORTD is output
  TRISC = $4000         ' PORT<14>=1 T1CK input pin
  LATD  = $0            ' Set initial value at port D
  IPC0  = IPC0 or $1000 ' Priority level is 1
  IEC0  = IEC0 or $0008 ' Timer1 interrupt enabled
  PR1   = 10            ' Interrupt period is 10 clocks
  T1CON = $8006         ' Timer1 is synchronous counter of external pulses

  while true            ' Endless loop
    nop
  wend
end.

How does one configure timer1 module to operate in the 16-bit synchronous mode? Prescaler ratio 1:1 is selected, external clock TCS = 1 is enabled, and operation of timer1 module TON = 1 is enabled (T1CON = $8006). By setting bit TRISC<14>=1 the pin PORTC<14>=1 is configured as input.

4.1.3 16-bit asynchronous counter mode

In the 16-bit asynchronous counter mode the counter value TMR1 increments on every rising edge of an external clock source, but the phase of the internal clock is not synchronized with the external clock. When the value of the TMR1 counter is equal to the preset value of the PR1 register, the counter TMR1 is reset and starts counting from ‘0’. At this moment an interrupt request for timer1 module T1IF (in the register IFS0) is generated. Processing of this request depends on the interrupt T1IE enable bit (in the IEC0 register). Timer module continues to operate during the interrupt routine.

The timer1 module could operate in this mode during IDLE state if bit TSIDL (T1CON<13>) is reset; if this bit is set, the counter continues operation after the processor is waken-up from IDLE state.

Example:

Count each 800th pulse and increment the value at port D. In this example timer1 is used to count each 8th pulse of an external clock at the external pin T1CK. After 100 pulses the interrupt routine Timer1Int is called and the value at port D is incremented. Block diagram of Fig. 4-3 shows the interconnection between the timer1 and external clock source.

Block diagram of the connection of an external clock source to dsPIC30F4013

Fig. 4-3 Block diagram of the connection of an external clock source to dsPIC30F4013

program TestTimer1
sub procedure Timer1Int org $1A ' Timer1 address in the interrupt vector table
  Inc(LATD)                ' Value at PORTD is incremented
  IFS0 = IFS0 and $FFF7    ' Interrupt request is reset
end sub
main:
  TRISD = 0               ' PORTD is output
  TRISC = $4000           ' PORT<14>=1 T1CK is input pin
  LATD  = $0              ' Set initial value at port D
  IPC0  = IPC0 or $1000   ' Priority level is 1
  IEC0  = IEC0 or $0008   ' Timer1 interrupt enabled
  PR1   = 100             ' Interrupt period is 100 clocks
  T1CON = $8012           ' Timer1 is synchronous counter of external pulses
  while true              ' Endless loop
    nop
  wend
end.

4.1.4 Gated timer mode

When timer1 module operates in the 16-bit timer mode, it can be configured to allow the measurement of duration of an external gate signal (gate time accumulation). In this mode the counter TMR1 is incremented by internal instruction clock (TCY) as long as the external GATE signal (pin T1CK) is at the high logical level. In order that timer1 module operates in this mode it is required that the control bit TGATE (T1CON<6>) is set, internal clock (TCS=0) is selcted, and the operation of the timer is enabled (TON=1).

The timer1 module could operate in this mode during IDLE state if bit TSIDL (T1CON<13>) is reset; if this bit is set, the counter continues operation after the processor is waken-up from IDLE state.

Example:

Use timer1 in the gated time accumulation mode.The enable GATE signal is applied to the pin T1CK. Measure the width of the signal and display the result at port D. Block diagram of interconnection of timer1 and an external clock source is shown in Fig. 4-4.

Block diagram of the connection of an external clock source to dsPIC30F4013

Fig. 4-4 Block diagram of the connection of an external clock source to dsPIC30F4013

program TestTimer1
sub procedure Timer1Int org $1A ' Timer1 address in the interrupt vector table
  LATD = TMR1             ' Pulse duration is displayed at port D
  IFS0 = IFS0 and $FFF7   ' Interrupt request is processed
end sub

main:
  TRISD = 0                ' PORTD is output
  TRISC = $4000            ' PORT<14>=1 T1CK is input pin
  LATD  = $0               ' Set initial value at port D
  IPC0  = IPC0 or $1000    ' Priority level is 1
  IEC0  = IEC0 or $0008    ' Timer1 interrupt enabled
  PR1   = $FFFF            ' Period is maximum
  T1CON = $8040            ' Timer1 is enabled, internal clock until T1CK=1

  while TRUE               ' Endless loop
   nop
  wend
end.

Why the register PR1 is set to the maximum value? The main reason is to allow measurement of as long as possible time intervals, i.e. the interrupt does not come as a consequence of equalisation of the TMR1 and PR1 registers but, if possible, as a consequence of the falling edge of the GATE signal.

In the operation of the timer1 module the applications often require the use of the prescaler which allows that the clock can be reduced by the ratio 1:1, 1:8; 1:64, or 1:256. In this way the scope of applications of the timer1 module is widened considerably. The prescaler selection is done by setting the control bits TCKPS<1:> (T1CON<5:4>). The prescaler counter is reset every time of writing in the counter register TMR1, or control register T1CON, or after microcontroller reset. However, it is important to note that the prescaler counter can not be reset when the timer1 module is interrupted (TON=0) since the prescaler clock is stoped.

Attention!
The counter register TMR1 is not reset when a new value is written in the control regster T1CON. The contents of the TMR1 register has to change after writing a new value in this register.

The operation of the timer1 module in SLEEP mode is possible only if the following conditions are fullfiled:

  • the operation of the timer1 module is enabled (TON=1),
  • timer1 module uses an external clock,
  • control bit TSYNCH (T1CON<2>) is reset defining an asynchronous external clock source. i.e. the clock is independent of the internal microcontroller clock.

In this way it is allowed that the timer1 module continues counting as long as the register TMR1 is equal to the preset (period) register PR1. Then, TMR1 is reset and an interrupt is generated. An interrupt request for the timer1 module, if the enable bit is set, can wake-up the microcontroller from SLEEP mode.

The timer1 module generates an interrupt request when the values of the counter register TMR1 and preset (period) register PR1 are equal. The interrupt request is effected by setting bit T1IF in the interrupt register IFS0. If the timer1 module interrupt enable bit T1IE in the interupt register IEC0 is set, an interrupt is generated. The bit T1IF has to be software reset in the interrupt routine.

If the timer1 module operates in the gated time accumulation mode, then the interrupt request will be generated at each falling edge of the external GATE signal, i.e. at the end of each accumulation cycle.

4.1.5 Real-Time Clock (RTC) operation mode

The timer1 module can be adjusted to operate in the Real-Time Clock operation mode, i.e. as a real time clock. In this way one obtains the information of the time instants (hours, minutes, seconds) serving for the evidence of events. The main characteristics of the RTC mode of operation of the timer1 module are: use of the 32kHz oscillator, 8-bit prescaler, low power, and the ability of generating an RTC interrupt request. Like all timer1 module operation modes, this mode is set by the control bits in the register T1CON. While the timer1 module uses the clock of the 32kHz oscillator for operation in the RTC mode, the remaining of the microcontroller has the ability to operate with another clock which is adjustable by the control bits in the control register FOSC.

In this mode, when the control bits are TON=1, TCS=1, and TGATE=0, the counter register TMR1 is incremented by each rising edge of the 32kHz low power oscillator until the value of the counter register TMR1 is equal to the preset value of the PR1 register; the counter register TMR1 is then reset t? '0'.

Attention!
In order that timer1 module operates correctly in the RTC mode, the control bit TSYNC has to be reset. By setting TSYNC=0 the asynchronous mode of the timer1 module is set. Also, the bit LPOSCEN (T1CON<1>) has to be set to disable all other operation modes except RTC and enable wake-up of the microcntroller from SLEEP state by the timer1 module. It is very important that the TSIDL bit is reset to allow operation of timer1 module during IDLE state.

With this configured timer1 module, in SLEEP state the TRC will continue operation clocked from the 32kHz oscillator and the control bits will not be changed.

When the condition for generation of an interrupt request is fulfilled (TMR1=PR1), the bit T1IF in the interrupt register IFS0 is set. If the corresponding interrupt is enabled (the enable bit T1IE in the IEC0 register is set), an interrupt of the microcontroller is generated. During the interrupt routine the bit T1IF has to be reset, otherwise no other interrupt request could be detected by timer1 module.

Connection of a crystal oscillator in the RTC mode

Fig. 4-5 Connection of a crystal oscillator in the RTC mode

name ADR 15 14 13 12-7 6 5 4 3 2 1 0 Reset State
TMR1 0x0100 Timer 1 Register 0x0000
PR1 0x0102 Period Register 1 0xFFFF
T1CON 0x0104 TON - TSIDL - TGATE TCKPS1 TCKPS0 - TSYNC TCS - 0x0000

Table 4-1 Registers of timer1 module

TON – Timer1 module on bit (TON=1 starts timer, TON=0 stops timer)
TSIDL – Stop in IDLE mode bit (TSIDL=1discontinue module operation when 
        microcontroller enters IDLE mode, 
TSIDL = 0 continue module operation in IDLE mode)
TGATE – Timer gated time accumulation mode enable bit (TCS must be set to logic 0 when TGATE=1)
TCKPS<1:0> - Timer input clock prescale select bits
        00 – 1:1 prescale value
        01 – 1:8 prescale value
        10 – 1:64 prescale value
        11 – 1:256 prescale value
TSYNC – Timer external clock input synchronization select bit 
(TSYNC=1 synchronize external clock input, TSYNC=0 do not synchronize external clock input)
TCS – Timer clock source select bit 
(TCS=1 external clock from pin T1CK, TCS=0 internal clock Fosc/4)

NOTE: Unimplemented bits read as ‘0’.

4.2 Type B timer

Type B timer is a 16-bit timer present in most devices of the dsPIC30F family of microcontrollers. It is denoted as the timer2 module and timer4 module like in dsPIC30F4013 microcontroller. Type B timer has the following specific features:

  • a type B timer can be concatenated with a type C timer to form a 32-bit timer,
  • the clock synchronization for a type B timer is performed after the prescaler.

Type B timer functional block diagram is shown in Fig. 4-6.

Type B timer functional block diagram (timer2 module)

Fig. 4-6 Type B timer functional block diagram (timer2 module)

4.3 Type C timer

Type C timer is a 16-bit timer. Most often it is used together with type B timer to form a 32-bit general purpose timer. Timers of this type, if present, in the dsPIC30F family of microcontrollers are denoted as the timer3 module and timer5 module like in dsPIC30F4013 microcontroller. Type C timer has the following specific features:

  • a type C timer can be concatenated with a type B timer to form a 32-bit timer,
  • at least one type C timer has the ability to trigger an A/D conversion.

Type C timer functional block diagram is shown in Fig. 4-7.

Type C timer functional block diagram (timer 3 module)

Fig. 4-7 Type C timer functional block diagram (timer 3 module)

Attention!
Pin T3CK does not exist in dsPIC30F4013 devices. The figure shows organization of the timer module of a dsPIC30F6014A device. Also, timer5 module does not have the ability to trigger an A/D conversion.

4.4 Concatenated 32-bit timer

The described type B and C timers, as already mentioned, could be concatenated to form a 32-bit timer. Functional block diagram of the concatenated 32-bit timer is shown in Fig. 4-8.

Type C timer functional block diagram (timer 3 module)

Fig. 4-8 Type C timer functional block diagram (timer 3 module)

The 32-bit timer of Fig. 4-8 is formed by combining the timer2 and timer3 modules. The timer4 and timer5 modules could be combined in a similar way. The formed 32-bit timer is a general purpose (GP) timer and could be configured by the control bits to operate in the following modes:

  • 32-bit timer.
  • 32-bit synchronous counter.

It is significant to note that the timer2 and timer3 modules could independently operate as 16-bit timers in the all operational modes as the timer1 module, except in the asynchronous counter mode. The same applies for timer4 and timer5 modules.

Timer2 and timer3 modules make use of other peripherals, Input capture or Output compare, in order to realize in a simple way a pulse-width modulated (PWM) signal or an A/D converter for triggering conversion at precise sampling times which is not possible with the timer4 and timer5 modules.

The concatenated 32-bit timer2/3 module has the ability to:

  • A/D event trigger,
  • operate in gated time accumulation mode,
  • prescaler select,
  • operate in IDLE state, and
  • generate an interrupt request upon the concatenated counter register TMR2/TMR3 is equal with the preset register PR3/PR2.

Adjustment of the mode of operation of the concatenated timer2/3 module is performed by the control bits in T2CON and T3CON.

Attention!
If the timer2 and 3 modules operate independently, the operation modes are adjusted by T2CON and T3CON. If they operate as the concatenated timer2/3 module, then the T2CON control bits are adjusted and T3CION control bits are ignored. The timer2 module clock and gate inputs are used for the concatenated 32-bit timer2/3 module. An interrupt of the 32-bit timer is generated with the T3IF flag and the corresponding T3IE enable bit.

4.4.1 32-bit timer mode

In the 32-bit timer mode the timer is incemented at each instruction cycle until the value of the concatenated counter register TMR3/TMR2 is equal to the concatenated preset register PR3/PR2. Then the counter register is reset to ‘0’ and an interrupt request is generated with the bit T3IF.

NOTE: Synchronous reading of the 32-bit TMR3/TMR2 register is carried out by reading timer2 module 16-bit TMR2 register as the Less Significant word (LS). During reading of TMR2 register the value of the TMR3 register is transferred to the temporary register TMR3HLD. The process of the 32-bit reading is concluded by reading the value of the Most Significant word (MS) from the register TMR3HLD.
The synchronous 32-bit writing is performed in two steps inversly to the reading. At first the higher significant word is written in the TMR3HLD and then the Less significant word is written in TMR2. During the writing in the TMR2 register the vaules of TMR3HDL and the counter register TMR3 are transferred to TMR2.

The following example demonstrates how the concatenated timer2 and 3 modules can be used in a 32-bit timer.

Example:

Turn on and off a LED diode at port D approximately once every two seconds. The example uses the concatenated timer2 and 3 modules having 256 times slower clock than that of the dsPIC device. At each 100 000 clocks of timer1 interrupt routine Timer23Int is called and the value at port D is changed.

program TestTimer23
sub procedure Timer23Int org $22 ' Address in the interrupt vector table of timer3
  LATD = not PORTD ' Invert port D
  IFS0 = 0         ' Clear interrupt request
end sub
main:
  TRISD = 0              ' Port D is output
  LATD  = $AAAA          ' Initial value at port D is set
  IPC1  = IPC1 or $1000  ' Timer3 priority is 1
  IEC0  = IEC0 or $0080  ' Timer3 interrupt enabled
  PR2   = 34464          ' Interrupt period is 100 000 clocks
  PR3   = $0001          ' Total PR3/2=1*65536 + 34464
  T2CON = $8038          ' Timer2/3 is enabled, internal clock is divided by 256
  while TRUE             ' Endless loop
    nop
  wend
end.

How does one set timer2/3 module to the 32-bit timer mode? The corresponding iterrupt bits, i.e. interrupt priority T3IPC=1, interrupt request bit T3IF=0, and interrupt enable bit T3IE=1 are set first (in the concatenated timer2/3 module interrupts are controlled by the control bits of the timer3 module and the operation of the timer2/3 module is controlled by the control bits of the timer2 module). Then the operation of the timer is activated TON=1, 32-bit operation is selected T32=1, and in this case the prescaler is configured for 1:256 ratio TCKPS<1:0>=11. The preiod register PR2/3 contains the value 100 000 distributed according to the formula PR3/2=PR3*65536 + PR2, PR3=1 and PR2=34464.

How does one calculate the period of interrupt calls? Let the internal clock be adjusted to 10MHz. The corrsponding period is 100ns. Since the clock is divided by 256 (the prescaler reduces the clock 1:256) to form the clock of the timer, it follows that 100ns*256 = 25600ns, i.e. 25.6µs. At each 100 000 clocks an interrupt is called, i.e at each 2.56s or approximately once every two seconds.

T = 100 000*25.6µs = 2.56s.

4.4.2 32-bit synchronous counter mode

In a 32-bit synchronous counter mode the concatenated timer TMR3/TMR2 is incremented on each rising edge of the external clock signal which is synchronized with the phase of the internal clock signal of the microcontroller. When the value of the counter register TMR3/TMR2 is equal to the preset value of the PR3/PR2 register, the content of the register TMR3/TMR2 is reset to ‘0’ and an interrupt request is set by the bit T3IF.

The following example demonstrates how the timer2/3 module can be used in the 32-bit synchronous counter mode.

Example:

Use the timer2/3 for counting the external clock pulses at pin T1CK. After 10 pulses an interrupt Timer23Int occurs and increments the value at port D. Block diagram of connecting the timer 2/3 to the external source of clock is shown in Fig. 4-9.

Block diagram of connecting the timer 2/3 of a dsPIC30F4013  to an external source of clock

Fig. 4-9 Block diagram of connecting the timer 2/3 of a dsPIC30F4013 to an external source of clock

program TesTimer23
sub procedure Timer23Int org $22 'Address in the interrupt vector table of timer3
  Inc(LATD)                  ' Increments the value of PORTD
  IFS0 = 0                   ' Clear interrupt request
end sub
main:
  TRISD = 0               'PORTD is output
  TRISC = $2000           'PORTC<13>=1 T2CK is input pin
  LATD  = $0              'Initial value at PORTL is set
  IPC1  = IPC1 or $1000   'Interrupt priority of timer3 is 1
  IEC0  = IEC0 or $0080   'Interrupt of timer3 enabled
  PR2   = 10              'Interrupt peiod is 10 clocks
  PR3   = 0               'Total PR3/2=0*65536 + 10
  T2CON = $800A           'Timer2/3 is synchronous counter of external pulses
  while TRUE              'Endless loop
   nop
  wend
end.

How does one set timer 2/3 module to the synchronous counter mode? Prescaler 1:1 is selected, external clock is enabled TCS=1, 32-bit operation is enabled T32=1, the operation of the timer1 module is enabled TON=1 in the control register T2CON (in 32-bit operation the control bits T3CON are ignored), interrupt bits of timer2/3 module are set (in the concatenated timer2/3 interrupts are controlled by the control bits of timer3 module), priority of interrupts T3IPC=1, interrupt request bit T3IF=0, and interrupt enable bit T3IE=1.

4.4.3 Gated time accumulation mode

The concatenated 32-bit timer module can be used in the gated time accumulation mode.This mode allows that the TMR3/TMR2 counter is incremented by the internal clock TCY as long as the state of the external GATE signal (pin T2CK) is high. In this way one can measure the length of the external signal. In order to operate the 32-bit timer in this mode, it is required to set the control bit TGATE (T2CON<6>) to enable this mode, select the clock source TCS=0, and enable timer operation TON=1 in the control register T2CON. In this mode the timer2 module is the internal clock source. Control bits of the timer3 T3CON are ignored.

The interrupt request is generated on the falling edge of the external GATE signal or when the value of the TMR3/TMR2 counter reaches the preset value in the PR3/PR2 register.

Attention! The falling edge of the external GATE signal does not reset the TMR3/TMR2 counter; if desired, this has to be done by the user software.

Example:

Use timer 2/3 in the gate time accumulation mode. GATE signal is applied to pin T1CK. The length of the signal is measured and displayed at pord D. Block diagram of the timer2/3 connection to an external clock sourse is shown in Fig. 4-10.

Block diagram of the timer2/3 connection to an external clock source

Fig. 4-10 Block diagram of the timer2/3 connection to an external clock source

program TestTimer23

sub procedure Timer2Int org $20 'Address in the interrupt vector table of timer2
  LATD = TMR2               'Signal length is displayed at port D
  IFS0.6 =0                 'Interrupt request cleared
end sub

main:
  T2CON = 0                 'Stops the Timer2 and reset control register
  TMR2  = 0                 'Clear contents of the timer register
  PR2 = $FFFF               'Load the Period register with $FFFF
  IFS0.6 = 0                'Interrupt request cleared
  T2CON.6 = 1               'Set up Timer2 for Gated time accumulation mode
  T2CON.15 = 1              'Start Timer2
  TRISD = 0                 'PORTD is output
  TRISC = $2000             'PORTC<13>=1 is input pin
  IEC0.6 = 1                'Timer2 interrupt enable
  while TRUE                'Endless loop
    nop
  wend
end.

Why the period registers PR2 and PR3 are set to the maximum value and how does one measure even longer pulses? The main reason is to measure as long pulses as possible, i.e. the interrupt does not occur because the concatenated registers TMR3/TMR2 and PR3/PR2 are equal but, if possible, it is the ceonsequence of the falling edge of the GATE signal. Measuring even longer pulses can be accomplushed by setting the prescaler to higher reduction ratios 1:8, 1:64, or 1:256. In this way the range of measurement is extended but the accuracy is reduced.

Description of the gated time accumulation mode of the 32-bit timer2/3 module

Fig. 4-11 Description of the gated time accumulation mode of the 32-bit timer2/3 module

The concatenated timer2/3 has the ability to trigger an A/D conversion. This is realized by setting the corresponding control bits in the register ADCON<7:5> (SSRC<2.0>=010). When the value of the concatenated counter register TMR3/TMR2 becomes equal to that of the PR3/PR2 register, the A/D converter is triggerred and an interrupt request is generated.

NOTE: The timer modules 2 and 3 could operate independently as 16-bit timers. They coud be configured to operate in the following modes: 16-bit timer, 16-bit synchronous counter, and 16-bit gated time accumulation. The timer modules 2 and 3 can not operate as 16-bit asynchronous counters nor as real time clock sources (RTC).

As a clock source, the timer2 and 3 modules use an external clock source or the internal clock FOSC/4 with the option of selecting the prescaler reduction ratio 1:1, 1:8, 1:64, or 1:256. The selection of the reduction ratio is achieved by the control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). When the timer2 and 3 modules form the concatenated 32-bit timer module, then the prescaler reduction ratio is selected by the timer2 module and the corresponding control bits of the timer3 module are ignored. The prescaler counter is reset only if: writing in the registers TMR2 or TMR3, writing in the registers PR2 or PR3, or the microcontroller is reset. It is important to note that the prescaler counter can not be reset when the timer1 module is disabled (TON=0) since the clock of the prescaler counter is stoped. Also, writing in T2CON/T3CON does not change the contents of TMR2/TMR3.

In SLEEP mode the timer2 and 3 modules are not functional since the system clock is disabled. In IDLE mode the timer2 and 3 modules will continue operation if TSIDL bit is cleared. If this bit is set, the timer2 and 3 modules will stop until the microcontroller is waken up from IDLE mode.

The characteristics of the timer4 and 5 modules are very similar to those of the timer2 and 3 modules. If concatenated to form a 32-bit timer, they could operate in the same modes as the timer2 and 3 modules. The only difference is that the timer4 and 5 modules are not used by other peripherals Iput capture and Output compare like the timer2 and 3 modules. Also, the timer5 module has no ability like the timer3 module to trigger an A/D conversion.

Pin diagram of dsPIC30F4013

Fig. 4-12a Pin diagram of dsPIC30F4013

Pin diagram of dsPIC30F6014A

Fig. 4-12b Pin diagram of dsPIC30F6014A

Finally, a description of the registers of the timer2, 3, 4, and 5 modules of microcontroller dsPIC30F4013 is presented.

name ADR 15 14 13 12-7 6 5 4 3 2 1 0 Reset State
TMR2 0x0106 Timer2 register 0x0000
TMR3HLD 0x0108 Timer3 holding register (32-bit operation only) 0x0000
TMR3 0x010A Timer3 register 0x0000
PR2 0x010C Period register 2 0xFFFF
PR3 0x010E Period register 3 0xFFFF
T2CON 0x0110 TON - TSIDL - TGATE TCKPS1 TCKPS0 T32 - TCS - 0x0000
T3CON 0x0112 TON - TSIDL - TGATE TCKPS1 TCKPS0 - - TCS - 0x0000

Table 4-2 Description of the registers of the timer2 and 3 modules

TON – Timer on control bit (TON=1 starts the timer, TON=0 stops the timer)
TSIDL – Stop in IDLE mode bit (TSIDL=1 discontinue timer operation when device enters 
        IDLE mode, TSIDL=0 continue timer operation in IDLE mode)
TGATE – Timer gated time accumulation enable bit (TCS must be set to 0 when TGATE=1)
TCKPS<1:0> - Timer input clock prescale select bits
      00 – 1:1 prescale valu
      01 – 1:8 prescale value
      10 – 1:64 precale value
      11 – 1:256 prescale value
T32 – Timer 32-bit mode of timer4 and 5 select bit (T32=1 32-bit mode selected, T32=0 timer2 
      and 3 modules operate in 16-bit mode)
TCS – Timer clock source select bit 
      (TCS=1 external clock from pin T1CK, TCS=0 internal clock FOSC/4)

NOTE: Reading unimplemented bits gives '0'.

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